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A. J. Acosta, M. Valencia, A. Barriga, M. J. Bellido, J. L. Huertas, "SODS: A New CMOS Differential-Type Structure",IEEE Journal of Solid State Circuits, v. 30, n. 7, pp. 835---838, July 1995

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Asynchronous Pipelined Datapaths Design Techniques. A Survey - Cornetta, Cortadella (1997)   (Correct)

....a twophase handshake protocol. On the contrary, FIFOs implementation use a four phase protocol. A non lineal FIFO is presented in [21] lineal architecturer are presented in [29, 30] In this section we will deal with several lineal implementations using a full handshake protocol and SODS logic [2] presented in [1] such implementations are basically an improvement of the architectures presented in [29, 30] Since the original implementation due to Meng could produce malfunction when the current pipeline stage was still processing and the previous stage entered the precharge phase, some new ....

A. J. Acosta, M. Valencia, A. Barriga, M. J. Bellido, J. L. Huertas, "SODS: A New CMOS Differential-Type Structure",IEEE Journal of Solid State Circuits, v. 30, n. 7, pp. 835---838, July 1995


Differential Current Switch Logic: A Low Power DCVS Logic Family - Dinesh Somasekhar   (2 citations)  (Correct)

....this topology. Enabled disabled CMOS differential logic (ECDL) proposed in [5] avoids the high power consumption of SSDL. ECDL employs a precharge low circuitry as shown in fig. 3. It avoids the static path present in the sample phase of SSDL. While there are other DCVS families reported [6] [7], the above families are representative of DCVS families with good propagation delay, area and power consumption. We use these topologies, namely clocked CVSL, SSDL, and ECDL as reference circuits for comparing gate power, gate propagation delay, transistor count and clock load. Each of the above ....

A. J. Acosta, M. Valencia, A. Barriga, M. J. Bellido, and J. L. Huertas, "SODS: A New CMOS Differential-Type Structure" IEEE J. Solid-State Circuits, vol. 30, No. 7, pp. 835-838, Jul 1995.

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