L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: a differential CMOS logic family," in Proc. Int. Conf. on Solid-State Circuits, 1984, pp. 16-17.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of dynamic logic styles in asynchronous designs [4] In [5] a divider using a ring structure was realized and yields no delay in addition to the evaluation time. Such self timed techniques require completion signals and, therefore, differential logic styles or dual rail realizations are used. In [6], Differential Cascode Voltage Switch Logic (DCVSL) was introduced (figure 1) It builds the starting point for several differential logic styles and was derived from two complementary DOMINO gates with merged logic trees. In this paper, the main goal is the usage of short self timed chains in ....

L. G. Heller, W. R. Griffin, J. W. Davis and N. G. Thoma, "Cascode Voltage Switch Logic: A Differential CMOS Logic Family", Proceedings of International Solid-State Circuits Conference, IEEE, 1984, pp. 16-17.

....efficiency, push pull type output driver, reliability. I. INTRODUCTION R ECENTLY, various logic styles have been introduced to implement high performance digital systems, replacing conventional static CMOS logic styles. Among them, some clocked CMOS differential logic structures were introduced [1] [5] They have high speed and low power characteristics due to small load capacitance using only the NMOS logic tree as in domino logic. Moreover, they can acquire high speed and good logic flexibility through the effective use of differential output signals. As energy efficiency becomes a more ....

....3) Other transistors in the precharge circuit are used in order to separate output loads and the NMOS logic tree. IV. PERFORMANCE COMPARISON To compare the performance of the proposed SPDL, we simulated some prelayout SPDL circuits and measured some postlayout ones with previously reported CVSL [1] and HRDL [4] It is difficult to compare the CRDL [3] with the SPDL because the CRDL uses special process parameters with high threshold PMOS transistors. Simulations are performed by HSPICE using 0.6 m CMOS parameters. Fig. 4 shows the simulated performance of a four input XOR gate according ....

L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 16--17.

....in a 0.6 m CMOS technology. Experimental results show that the critical path delay is 3.5 ns with a power consumption of 27 mW at 50 MHz. I. INTRODUCTION A LARGE number of CMOS differential logic families have been introduced for applications in low power and high speed logic systems [1] [6] The main stream underlying the evolution of these differential logic families is to employ an acceleration circuit in order to reduce the large RC delay, which increases with the tree height of the nMOS transistors. Although the driving capability of a complex logic function implemented in ....

L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 16--17.

....use of dynamic logic styles in asynchronous designs. In [5] a divider using a ring structure was realized and yields no delay in addition to the evaluation time. Such self timing techniques require completion signals and therefore, differential logic styles or dual rail realizations are used. In [7], Cascode Voltage Switch Logic (DCVSL) was introduced as a differential logic (figure 1) which built the starting point for several new logic styles. It was derived from two DOMINO logic blocks with complementary functions, merged logic trees, and a shared clocked N transistor. Complex logic ....

L. G. Heller, W. R. Griffin, J. W. Davis and N. G. Thoma, Cascode Voltage Switch Logic: A Differential CMOS Logic Family. Proceedings IEEE International Solid-State Circuits Conference, 1984, pp. 16-17.

....certain circuits can account for some 30 of the energy requirement [2] are eliminated. However, because a domino stage can implement only non inverting functions, dynamic carry save array (CSA) multipliers have traditionally used less energy efficient, differential techniques [3] such as DCVSL [4]. The energy savings of dynamic logic are further offset by the need to charge and discharge the precharge evaluate lines. This normally takes place once per cycle although with the conditional evaluation technique reported here, for parts of the circuit it can happen less frequently. More ....

L.G. Heller and W.R. Griffin, "Cascode Voltage Switch Logic: A Differential CMOS Logic Family," ISSCC Dig. Tech. Papers (New York), pp.16-17, Feb. 1984.

....and the number of tracks required by the chosen topology, one uses either single ended or complementary signal circuits. Single ended signals include both the static or pass transistor logic families [10] While the fast complementary signal circuits include the domino [11] NORA [12] and CVSL [13] logic families. An expanded discussion about the merits and disadvantages of each logic family when implementing counters can be found in Song[14] For the topologies chosen, higher order arrays were implemented in domino logic, while all other topologies used a combination of static and pass ....

L. Heller, W. Griffin, J. Davis and N. Thomas, "Cascode Voltage Switch Logic: A differential CMOS Logic Family", IEEE International Solid State Conference, pp. 1619, Feb. 1984.

....and the interconnection requirements of the structure chosen, one uses either single ended or complementary signal circuits. Single ended signals include both the static or pass transistor logic families [9] While complementary signal circuits include both the domino [10] NORA[11] and CVSL[12] logic families. The static logic uses NMOS and PMOS transistor trees. These trees are never simultaneously active in steady state, and have no steady state power dissipation. The pass transistor logic family uses NMOS or NMOS PMOS transistors for steering the input to the output, and an inverter ....

L. Heller, W. Griffin, J. Davis and N. Thomas, "Cascode Voltage Switch Logic: A differential CMOS Logic Family", IEEE International Solid State Conference, pp. 1619, Feb. 1984.

....instead of individual paths. The notions and techniques developed in this context are not only of interest in the context of universal test sets but also for more general settings [30] There are various applications of our results. The first one is for testing of dynamic CMOS logic [31] 32] [33], which is often applied in high speed circuits [34] and must be structured as a unate gate network. Also self checking circuits based on unordered codes, are usually built as UGNs [35] 36] Another application is in synthesis for delay fault testability. Any circuit can be transformed into a ....

L.G. Heller, W.R. Griffin, J.W. Davis, and N.G. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in Proceedings of the IEEE International Solid State Circuits Conference, 1984.

....is in most cases not sufficient for verifying the temporal correctness of UGNs, i.e. path system testing is really necessary for a complete delay test of these circuits. The result of [SMR94] has several important applications. The first one is for the testing of dynamic CMOS logic [KLL82, GD83, HGDT84] which is often applied in high speed circuits [PDY92] and must be structured as a unate gate network. Also self checking circuits based on unordered codes are usually built as UGNs [DWB92, JW93] Finally, the result can be applied in synthesis for testability. Any combinational circuit can be ....

L.G. Heller, W.R. Griffin, J.W. Davis, and N.G. Thoma. Cascode voltage switch logic: A differential CMOS logic family. In IEEE International Solid State Circuits Conference, 1984.

....detector at the output of QDL. III. Implementation and Experimental Results In general, self timed logic employs a dual rail encoding to generate a completion signal when the functional block finishes its evaluation. QDL can be designed using DCVSL(Differential Cascode Voltage Switch Logic)[15]. However, the circuit is relatively complex, and therefore does not yield an easy optimization. As mentioned above, each quotient digit needs two values, aq aq and sq aq, for binary RSD number representation. The two values are generated by QDL s two circuits, AQ generator and SQ generator, ....

L. G. Heller and W. R. Griffin, "Cascode voltage switch logic: A differential CMOS logic family", in ISSCC Digest of Technical Papers, New York, Feb. 1984, pp. 16--17.

....F F OUT OUT Differential Buffer (a) OUT OUT F F (b) F F OUT OUTCLK CLK CLK (c) Figure 8: DPTL Logic Family: a) 2 Input AND Gate, b) Static Differential Buffer, c) Clocked Differential Buffer. The static buffer is simply a differential cascode voltage switch logic (DCVSL) inverter [11, 17]; the clocked buffer is basically a DRAM sense amplifier [18] B B A B A A B A A B A B (a) B A B B A A A A B B B A B A B A A B A B (b) B A B A B A B A AB AB (c) C C C C A B A B A A B B O O (d) Figure 9: CPL Logic Gates: a) 2 Input OR NOR Gate, b) 2 Input EXOR EXNOR Gate, c) 2 Input ....

....be as big as possible, while the transistor forming the latch should have to be of minimum size. Figure 10 shows the structure of a generic SRPL gate. NMOS CPL network F F Figure 10: Basic SRPL Gate. 2. 3 Differential Cascode Voltage Switch Logic (DCVSL) Differential cascode voltage switch logic [17, 7, 8], may be either static or dynamic. It is formed by a NMOS differential network where the input signals appear both in direct and complemented form and by a pair of cross coupled pull up PMOS transistors. NMOS combinational network F F Differential inputs (a) NMOS combinational network ....

L. G. Heller, W. R. Griffin, J. W. Davis, N. G. Thoma, "Cascode Voltage Switch Logic: A Differential CMOS Logic Family", IEEE International Solid State Circuits Conference, pp. 16---17, February 1984.

....ADD SUB unit complete its output within a certain delay after all group s carry signals are generated. The structure of the MUL functional unit is a WallaceTree and generate 32 bit result from two 32 bit inputs. Each half full adder is implemented by Differential Cascode Voltage Switch Logic, DCVSL[6] synthesized from BDD specification[11] DCVSL circuit s precharge (evaluation) signal wires and buffers are placed like the H tree for isochronic signal transition. The DIV functional unit gets 32 bit dividend and 32bit divisor and generate 32 bit result using the restoring method. Usually, carry ....

W. R. G. Lawrence G. Heller. Cascode voltage switch logic: A differential cmos logic family. IEEE International Solid-- State Circuits Conference, Digest of Technical Papers:16-- 17, February 1984.

....cmos, design, high performance, low voltage, low power dissipation. I. INTRODUCTION Unlike conventional CMOS circuit designs which use low functionality gates with limited fan in, differential cascode voltage switch circuits (DCVS) allow much higher functionality with greater fan in [1] 2] [3]. This is especially true for DCVS logic styles which use internal sense circuits (a cross coupled inverter pair) to speed output transitions, as in the case of Enable Disable Cascode voltage switch logic (ECDL) 5] 7] Sample Set Differential Logic (SSDL) 4] Latched differential cascode Logic ....

L. G. Heller, W. R. Griffin, J. W. Davis and N. G. Thomas, "Cascode voltage switch logic: A differential CMOS logic family, " in Proc. IEEE Int. Solid-State Circuits Conf., 1984, pp. 16-17.

....differ primarily in the output stage. While it is possible to have a static DCVS gate by employing static PMOS pull ups at the output nodes, clocked DCVS gates are in general preferred because of their better performance. The simplest clocked DCVS gate is the clocked CVSL gate shown in fig. 1 [3]. The output 2 Q Q CLK CLK INPUTS NMOS TREE Fig. 1. Clocked CVSL CLK Q Q INPUTS TREE NMOS Fig. 2: SSDL [4] Q Q CLK INPUTS NMOS TREE Fig. 3: ECDL [5] structure uses PMOS precharge transistors to pull the inverter inputs high during the low phase of the clock. Outputs are evaluated in the high ....

....output stage of figure 4 is used. To ensure safe operation, clock to T10 in figure 4 is a delayed version of the 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 4.0 4.0 4.0 4.0 4.6 4.6 5.2 5. 2 DCSL Output DCSL Output CO CO A[0] A[1] A[1] A[2] A[0] A[2] A[3] A[3] S S CY CY CI CI Fig. 14. A DCSL 4 2 compressor actual clock. This DCSL output stage has 12 transistors. Hence the reduction in output stages reduces the transistor complexity significantly. A simple algorithm was used to generate the NMOS tree from the 4 2 truth table. The final 4 2 ....

[Article contains additional citation context not shown here]

L. G. Heller, W. R. Griffin, J. W. Davis and N. G. Thomas, "Cascode voltage switch logic: A differential CMOS logic family, " in Proc. IEEE Int. Solid-State Circuits Conf., 1984, pp. 16-17.

No context found.

L. G. Heller, W. R. Griffin, J. W. Davis, and N. G. Thoma, "Cascode voltage switch logic: a differential CMOS logic family," in Proc. Int. Conf. on Solid-State Circuits, 1984, pp. 16-17.

No context found.

L. Heller, W. Griffin, J. Davis, and N. Thoma, "Cascode voltage switch logic: A differential CMOS logic family," in Proc. Int. Solid-State Circuit Conf. ISSCC'84, San Francisco, CA, 1984, pp. 16--17.

No context found.

L. Heller, et al., "Cascode Voltage Switch Logic: a Differential CMOS Logic Family,

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