W. Lee, U. Ko, and P. Balsara, "A Comparative Study on CMOS Digital Circuit Families for Low-Power Applications," Proceedings of the 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 129-132, April 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....cascode logic circuits in favor of traditional CMOS styles. The high activity of DCVS gates and the need to route differential signals cause them to compare unfavorably with respect to implementations using static CMOS , complementary pass transistor logic, and differential pass transistor logic [1, 2]. However DCVS gates do offer the potential of having high fan in which leads to a reduction in logic depth, high speed, and the capability of generating completion signals for asynchronous operations. We hope that the advantages of DCSL in these areas would merit a second look at these gates. 1 ....

Wai Lee, Uming Ko and P.T. Balsara, "A Comparative Study on CMOS digital Circuit Families for Low-Power Applications", Proceedings of the Intl. Workshop on Low Power Design 1994, pp. 129-131

.... circuit, cmos, design, high performance, low voltage, low power dissipation. I. INTRODUCTION Unlike conventional CMOS circuit designs which use low functionality gates with limited fan in, differential cascode voltage switch circuits (DCVS) allow much higher functionality with greater fan in [1], 2] 3] This is especially true for DCVS logic styles which use internal sense circuits (a cross coupled inverter pair) to speed output transitions, as in the case of Enable Disable Cascode voltage switch logic (ECDL) 5] 7] Sample Set Differential Logic (SSDL) 4] Latched differential ....

Wai Lee, Uming Ko and P.T. Balsara, "A Comparative Study on CMOS digital Circuit Families for Low-Power Applications", in Proceedings of the Intl. Workshop on Low Power Design , 1994, pp. 129-131.

....C IRCUIT design techniques have largely overlooked differential cascode logic circuits in favor of traditional CMOS styles. This is mainly because the high activity of DCVS gates cause them to compare unfavorably with respect to conventional CMOS implementations from a power perspective [1]. The need to route differential signals, and the high clock load of clocked DCVS styles are known disadvantages [1] 2] However this sort of logic has potential advantages as compared to standard CMOS NAND(NOR) implementations. ffl High complexity, high fan in gates are possible. Complex gates ....

....CMOS styles. This is mainly because the high activity of DCVS gates cause them to compare unfavorably with respect to conventional CMOS implementations from a power perspective [1] The need to route differential signals, and the high clock load of clocked DCVS styles are known disadvantages [1], 2] However this sort of logic has potential advantages as compared to standard CMOS NAND(NOR) implementations. ffl High complexity, high fan in gates are possible. Complex gates can be implemented with lower transistor count. Certain clocked DCVS families have very low propagation delay for ....

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Wai Lee, Uming Ko and P.T. Balsara, "A Comparative Study on CMOS digital Circuit Families for Low-Power Applications", in Proceedings of the Intl. Workshop on Low Power Design , 1994, pp. 129-131.

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W. Lee, U. Ko, and P. Balsara, "A Comparative Study on CMOS Digital Circuit Families for Low-Power Applications," Proceedings of the 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 129-132, April 1994.

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