K. So, V. Zecca, "Cache Performance of Vector Processors," in Proc. of 15-th International Symposium on Computer Architecture, pp 261-268, Honolulu, Hawaii, May 1988. Home/Search Document Not in Database Summary Related Articles Check |
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Cache Performance in Vector Supercomputers - Kontothanassis, Sugumar.. (1994) (13 citations) (Correct)
....Because bandwidth overhead is higher in the cacheless system, the overall improvement due to better bandwidth is higher than the improvement due to lower latency. 4 Related work Vector caches have been studied previously by a number of researchers using miss ratios as the main performance metric [1, 3, 11]. Our work reports miss ratios similar to those observed by those studies, i.e. predominantly unit stride applications have lower miss ratios than applications with a lot of non unit stride references) but also provides the correlation of miss ratios with run time which is the ultimate system ....
K. So and V. Zecca. Cache Performance on Vector Processors. In Proceedings of the Fifteenth International Symposium on Computer Architecture, pages 261--268, Honolulu, HI, June 1988.
An Empirical Study of Cross-loop Reuse in the NAS benchmarks - Keith Cooper (1995) (2 citations) (Correct)
....programs, the use of cross loop reuse information has the potential to reduce useless prefetches by a factor of 2, which is fairly significant. 6 Related work There is an extensive body of previous research on memory reference behavior and cache performance of various benchmark applications [GHPS91, CP90, SZ88, Smi82]. These studies tend to focus on examining the effects of various architectural features (line size, associativity, etc) on cache performance, however, and do not try to classify or categorize the various sources of reuse. A number of researchers have developed compiler techniques useful for ....
K. So and V. Zecca. Cache performance of vector processors. In Proceedings of the 15th International Symposium on Computer Architecture, 1988.
Using A Cache In Place Of A Cedar-Like Vector Prefetch Unit - Seddighnezhad (1993) (Correct)
....time at which prefetching can be performed in a parallel program and shows that by using compile time analysis and software prefetching, data needed within an iteration of the loop can be fetched one or more iterations ahead. Therefore data would be available when they are needed. Zecca and So [22] have looked at cache performance for vector processors and have shown that understanding the memory access patterns for real applications is very important. They have studied the scalar and vector versions of programs and tried to determine the effects of vectorization on cache performance and ....
K. So and V. Zecca. Cache performance of vector processors. IEEE Transactions on Computers, pages 261--268, 1988.
A Vector Memory System Based on Wafer-Scale Integrated - Memory Arra Ys (Correct)
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K. So, V. Zecca, "Cache Performance of Vector Processors," in Proc. of 15-th International Symposium on Computer Architecture, pp 261-268, Honolulu, Hawaii, May 1988.
Efficient Implementation Techniques for Prime-Degree.. - Memory Systems Tzi-Cker (Correct)
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K. So, V. Zecca, "Cache Performance of Vector Processors," in Proc. of 15-th International Symposium on Computer Architecture, pp 261-268, Honolulu, Hawaii, May 1988.
Loop Optimization Techniques On Multi-Issue Architectures - Kaiser (Correct)
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K. So, V. Zecca, Cache Performance of Vector Processors, Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988, pp. 261268.
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