B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....it is always better to have one single reuse circuit instead of two or more. This means that we should only consider Hamiltonian reuse circuits. This is interesting because Hamiltonian reuse circuits result in register allocation schemes that can be directly implemented on rotating register files [ELM95, RLTS92]. This however may not be a good solution when also the unrolling degree for achieving such a register allocation is taken into account. In the case of an Hamiltonian circuit and no rotating register file on the processor, then the unrolling degree (and consequently the code size duplication ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register Allocation for Software Pipelined Loops. SIGPLAN Notices, 27(7):283--299, July 1992. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

....iterations of the loop. For each loop variant variable a new value is generated in each iteration of the loop and thus has a different lifetime. The maximum number of simultaneously live values (MaxLive) is a ralatively accurate approximation of the number of registers required for the schedule [27]. The critical cycle is defined as the scheduling cycle in which the number of live values is highest. The lifetime of a variable last from its definition to its final use. The lifetime of a variable can be divided into severals sections (called uses) whose lifetime goes from the previous use to ....

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....some constraints that prevent the use of these techniques for register allocation. For instance, the lifetime of loop variables may cross the boundary of iterations and may last for more than one iteration, interfering with themselves. Several proposals have been made to handle these constraints [15, 16, 27]. The main drawback of these aggressive scheduling techniques is their high register requirements [22, 24] This has motivated some recent modulo scheduling proposals whose main objective is the minimization of the register pressure [12, 14, 17, 20, 23] Figure 1a (dashed lines) shows the ....

....is small, the percentage of time is important. For instance, only 8 14 of the loops require more than 32 registers but they represent 34 45 of the total execution time. Having a schedule that uses more registers than those available in the target architecture requires some additional actions [27]. One of the options is to reschedule the loop with a reduced execution rate (i.e. with less iteration overlapping) this reduces the number of overlapped operations and variables. Unfortunately, the register reduction is at the expense of a reduction in performance. Another option is to spill ....

[Article contains additional citation context not shown here]

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....studied in the framework of acyclic schedules [5, 7, 8, 9] based on the original graph coloring proposal [10] However, software pipelining imposes some constraints that prevent the use of these techniques for register allocation. Although there have been proposals to handle these constrains [15, 16, 26], none of them deals with the addition of spill code (and its scheduling) that is needed to reduce the register pressure in software pipelined loops. Any software pipeliner fails when it generates a schedule that requires more registers than those available in the target machine. In this case, ....

....to reduce the register pressure in software pipelined loops. Any software pipeliner fails when it generates a schedule that requires more registers than those available in the target machine. In this case, some additional actions have to be performed in order to alleviate the high register demand [26]. One of the options is to reschedule the loop with a reduced execution rate (i.e. with less iteration overlapping) this reduces the number of overlapped operations and variables. Unfortunately, the register reduction may be at the expense of a reduction in performance. Another option is to spill ....

[Article contains additional citation context not shown here]

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....is a very important technique to yield better schedules, it is mostly performed on an intermediate code level, before the actual scheduling and register allocation phases in the compiler. Therefore, we will not discuss software pipelining techniques in depth. The interested reader is referred to [50, 65, 64, 36, 63] for some speci c algorithms or to [1, 54] for a broader discussion. 4.6 ILP Hardware Issues The possible ILP is determined in the rst place by the hardware: the number of register and functional units, the number of write back ports to the register le, store bu ers between the caches and main ....

Rau, B., Lee, M., Tirumalai, P., and Schlansker, M. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (June 1992), pp. 283-299.

....Eichenberger e.a. 3] however, both approaches do not always nd a solution and are not guaranteed to nd the optimum. Another approach using heuristics for register allocation which exploits special hardware features like predicated execution and rotating register les, is proposed by Rau e.a. [13]. Ning e.a. model symbolic registers that are organized as FIFOs and formulate an ILP problem to minimize the bu er size required [12] Their register constraints, however, are approximated to get linear expressions for the ILP solver. The reduction of the total number of registers is done in a ....

B.R. Rau, M. Lee, P.P. Tirumalai, and M.S. Schlansker. Register allocation for software pipelined loops. Conf. PLDI, 27(7):283-299, 1992.

....operations early with the aim of reducing the register requirements and achieving maximum execution rate. The algorithm integrates recurrence constraints and critical path considerations in order to decide when each operation is scheduled. The algorithm is based on Iterative Modulo Scheduling [6] [23] in the sense that uses a limited amount of backtracking in order to eject operations already scheduled to give place to a new one. Hypernode Reduction Modulo Scheduling (HRMS) 11] is a heuristic strategy that tries to shorten loop variant lifetimes. In HRMS the ordering of nodes is done so that ....

....a limited number of registers and the register allocator fails to find a solution with the number of registers available, some additional actions must be taken. Different alternatives to fit the register requirements of a modulo scheduled loop in the available number of registers were outlined in [23]. One of the options, used by the Cydra 5 compiler [6] is to reschedule the loop with an increased II . If, after several trials, the compiler is unable to find a valid schedule requiring less registers than available, the compiler schedules the loop using local scheduling techniques, i.e. ....

[Article contains additional citation context not shown here]

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker, "Register allocation for software pipelined loops," in Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, June 1992, pp. 283--299.

....b) and c) two alternative CCM organizations. The explicit management of these data movements requires modifications in the algorithm used for register allocation and spilling. The proposed algorithm first allocates registers in R1 using the wands only strategy with end fit and adjacency ordering [21]. If there are not enough registers in R1, spill code between R1 and R2 is inserted. Spill code is added using the techniques proposed in [28] and using only the loadR and storeR instructions. Once the register allocation and spill is completed for R1, the algorithm proceeds with R2. In R2 the ....

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....iterations of the loop. For each loop variant variable a new value is generated in each iteration of the loop and thus has a different lifetime. The maximum number of simultaneously live values (MaxLive) is a ralatively accurate approximation of the number of registers required for the schedule [27]. The critical cycle is defined as the scheduling cycle in which the number of live values is highest. The lifetime of a variable last from its definition to its final use. The lifetime of a variable can be divided into severals sections (called uses) whose lifetime goes from the previous use to ....

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....is issued. Figure 3.d shows the register requirements for this schedule; for each cycle it shows the number of live values required by the schedule. The number of registers required can be approximated by the maximum number of simultaneously live values at any cycle, which is called MaxLive (in [33] it is shown that register allocation never required more than MaxLive 1 registers for a large number of loops) In Figure 3.d, MaxLive=11. Notice that with this approach, variables generated by nodes n2 and n9 have an unnecessary large lifetime due to the early placement of the corresponding ....

....Regarding the second factor, if MaxLive is not higher than the number of available registers then the computed schedule is feasible and then it does not influence the execution time. Otherwise, some action must be taken in order to reduce the register pressure. Some possible solutions outlined in [33] and evaluated in [22] are: Reschedule the loop with an increased II. In general, increasing the II will reduce MaxLive but it decreases the issue rate. Add spill code. This again has a negative effect since it increases the required memory bandwidth and it will result in more memory ....

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B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283-299, June 1992.

....pipelining are scheduling techniques which have been used to improve performance on statically scheduled architectures. These techniques could be combined in a single compiler. Loop unrolling is generally used with trace scheduling [46] and loop unrolling has been used with software pipelining [149]. However, trace scheduling and software pipelining have not been combined, probably because of the complexity of these techniques. 1 Loop Unrolling Loop unrolling works by replicating the body of a loop some (machine and code dependent) number of times and scheduling the resulting code as a ....

....tend to have wide instructions with constrained resources and operations with long latencies. Software pipelining fits these architectures quite well, although hardware support for software pipelining does help [87] This idea is expanded and generalized by Rau et al. in [141] 142] 144][149]. Software pipelining appears to be a successful scheduling technique, one which needs to be at least be considered in an optimizing compiler. However, its promise is tempered by that fact that it places heavy demands on machine resources, particularly instruction cache and registers. 65 ....

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B. R. Rau, M. Lee, P. P. Tirumalai, M. S. Schlansker, Register Allocation for Software Pipelined Loops, R. L. Wexelblats (Ed.), Proceedings of the SIGPLAN '92 Conference on Programming Language Design and Implementation, 1992, vol. 27, pp. 283-299.

....there must be some mechanism to di erentiate among live instances of a variable de ned in previous iterations and the de nition in the current iteration. Two common schemes that support this form of register naming are modulo variable expansion (MVE) 15] and the rotating register le (RR) [21][22] MVE is a software only approach which gives each simultaneously live variable instance its own name, unrolling the loop body as necessary to insure that any later uses can directly specify the correct instance (more on this later) MVE both increases the architected register requirements and ....

....unnecessary and the loop kernel is not expanded from its original form. RR can therefore eliminate the code expansion problem from SP, but it still requires a large number of architected registers because all of the physically addressable registers are part of the architected rotating register le [21]. The problem of increasing a limited architected register space without dramatically changing an existing instruction set has also been explored. The Register Connection (RC) 14] method tolerates high demand for the architected registers by adding a set of extended registers to the core ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283-299, June 1992.

....source code for register allocation and to write a brief description of the algorithm used for register allocation in that compiler, including the generation of spill code. Software Pipelining After the students were introduced to software pipelining and rotating registers in class [DT93, DHB89, BRRS92] they were given a simple piece of code (an inner product computation) and were asked to compile the code both in Trimaran and in the Pro64, with software pipeline enabled and disabled. They were then asked to hand analyze the four versions of the code to estimate the number of cycles that each ....

P. P. Tirumalai B. R. Rau, M. Lee and M. S. Schlansker. Register allocation for software pipelined loops. In Proceedings of the SIGPLAN '89 Conference on Programming language design and implementation, pages 283--29, San Francisco, CA, June 1992.

....Regarding the second factor, if MaxLive is not higher than the number of available registers then the computed schedule is feasible and then it does not influence the execution time. Otherwise, some actions must be taken in order to reduce the register pressure. Some possible solutions outlined in [24] and evaluated in [16] are: ffl Reschedule the loop with an increased II . In general, increasing the II reduces MaxLive but it decreases the issue rate, which has a negative effect on the execution time. ffl Add spill code. This again has a negative effect since it increases the required memory ....

....to every iteration of the loop. By overlapping the lifetimes of the different iterations, a pattern of length II cycles that is indefinetely repeated is obtained. This pattern is shown in Figure 2c. This pattern indicates the number of values that are live at any given cycle. As it is shown in [24], the maximum number of simultaneously live values MaxLive is an accurate approximation of the number of register required by the schedule 2 . In this section, the register requirements of a given schedule will be approximated by MaxLive. However, in the experiments section we will measure the ....

[Article contains additional citation context not shown here]

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....de Cooperaci on Internacional. ules [15] 16] 17] 18] based on the original graph coloring proposal [19] However, software pipelining imposes some constraints that inhibit the use of these techniques for register allocation. Although there have been proposals to handle them [20] 21] [22], none of the proposals deals with the addition of spill code (and its scheduling) that is needed to reduce the register pressure in software pipelined loops. Any software pipeliner fails if it generates a schedule that requires more registers than those available in the target machine. In this ....

....to reduce the register pressure in software pipelined loops. Any software pipeliner fails if it generates a schedule that requires more registers than those available in the target machine. In this case, some additional actions have to be performed in order to alleviate the high register demand [22]. One of the options is to reschedule the loop with a reduced execution rate (i.e. with less iteration overlapping) this reduces the number of overlapped operations and variables. Unfortunately, the register reduction may be at the expense of a reduction in performance. Another option is to ....

[Article contains additional citation context not shown here]

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker, "Register allocation for software pipelined loops," in Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, June 1992, pp. 283--299.

.... [95] Modulo scheduling has also been extended to 57 a large variety of loops with early exits, such as while loops [87] 89] Furthermore, the code expansion due to modulo scheduling can be eliminated by using special hardware, e.g. support for rotating register files and predicated execution [82]. Since modulo scheduling exploits a higher level of parallelism, it results in higher register requirements because more values are needed to support more concurrent operations. This effect is inherent to parallelism in execution and will be exacerbated by wider machines and higher latency ....

....kind are issued in each row of the MRT. The MRT can also model specialized resources by allowing only certain types of operations in each column. The schedule of an iteration can be divided into stages of II cycles each. The number of stages in an iteration is referred to as the stage count (SC) [82] and corresponds to the maximum number of concurrent iterations in a modulo schedule. Figure 3.1b depicts the 4 stages associated with the schedule of Example 3.1. We notice that indeed the number of concurrent iterations never exceeds 4 in the execution trace depicted in Figure 3.1c. In general, ....

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B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....been extensively studied in the framework of acyclic schedules [3, 5, 6, 7] based on the original graph coloring proposal [8] However, software pipelining imposes some constraints that inhibit the use of these techniques for register allocation. Although there have been proposals to handle them [13, 14, 24], none of them deals with the addition of spill code (and its scheduling) that is needed to reduce the register pressure in software pipelined loops. Any software pipeliner fails if it generates a schedule that requires more registers than those available in the target machine. In this case, some ....

....to reduce the register pressure in software pipelined loops. Any software pipeliner fails if it generates a schedule that requires more registers than those available in the target machine. In this case, some additional actions have to be performed in order to alleviate the high register demand [24]. One of the options is to reschedule the loop with a reduced execution rate (i.e. with less iteration overlapping) this reduces the number of overlapped operations and variables. Unfortunately, the register reduction may be at the expense of a reduction in performance. Another option is to spill ....

[Article contains additional citation context not shown here]

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....lifetimes can cross the back edge of the loop i.e. they start in one iteration and finish in the next iteration. When this situation arises, traditional register allocators based in graph coloring perform poorly. New heuristics have been proposed that deal better with cyclic lifetimes [HGAM92, RLTS92, ELM95] Moreover, lifetimes are often much larger than the initiation interval. Normally, this would result in a value being overwritten before its last use has occurred. One solution is to unroll the kernel of the software pipelined loop a sufficient number of times and perform software ....

....allocator works with vector lifetimes, that is, the entire sequence of (scalar) lifetimes defined by a particular operation over the whole execution of the loop. Several heuristics for allocating vector lifetimes with and without rotating register files have been proposed and studied in [RLTS92] The meeting graph [ELM95] has been proposed to represent the vector lifetimes together with temporal information. With the meeting graph optimal unrolling for modulo variable expansion an optimal register allocation with rotating register files can be performed. If hardware support is provided ....

[Article contains additional citation context not shown here]

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....loop scheduling. It derives a static parallel schedule a periodic pattern that overlaps instructions from different iterations of a loop body. Software pipelining has been successfully applied to highperformance architectures [1] 2] 3] 4] 5] 6] 7] 8] 9] 10] 11] 12] [13], 14] Today, rapid advances in computer architecture hardware and software technology R. Govindarajan is with the Supercomputer Education and Research Center, and Department of Computer Science and Automation, Indian Institute of Science, Bangalore, 560 012, India. Email: ....

....rate optimal schedules under resource constraints, and illustrate how to search among them the ones which optimize the register usage. A more rigorous introduction to these concepts will be given in the next section. We adopt as our motivating example the loop L in Figure 1 given by Rau et al. in [13]. Both C language and instruction level representations of the loop are given in Fig. 1(b) while the dependence graph is depicted in Figure 1(a) Assume that instruction i 0 is 2 For a small number of test cases, less than 4 , the ILP schedule was worse in terms of either initiation rate or ....

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B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker, "Register allocation for software pipelined loops," in Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation, (San Francisco, California) , pp. 283--299, June 17--19, 1992. SIGPLAN Notices, 27(7), July 1992.

....locations to distinct queues. We have found through experimental analysis that using a queue register file may reduce dramatically the pressure on the name space, as shown in Section 4. ffl Register Allocation: The problem of register allocation, either considering a conventional register file [22] or a partitioned one [11] has been pointed out by several authors as being a non trivial task. We have developed a simple and efficient strategy to allocate data values to queues that we understand as being simpler than most of the techniques described in the literature. The scheme relies on a ....

B. Rau, M. Lee, P. Tirumalai, and M. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 - Conference on Programming Language Design and Implementation, June 1992.

.... Word (VLIW) and superscalar machines [1, 2, 3] Software pipelining has been proposed for exploiting ILP within loops, which can effectively overlap the execution of operations from different iterations [4, 5, 6, 7, 8, 9, 10, 11, 12] Register Allocation is another key compilation issue [13, 14, 15, 16, 17]. It has been well known that performing register allocation before software pipelining may introduce unacceptable anti dependences due to the reuse of registers, which may limit software pipelining [17, 3] On the other hand, if software pipelining is done before register allocation, more ....

.... 6, 7, 8, 9, 10, 11, 12] Register Allocation is another key compilation issue [13, 14, 15, 16, 17] It has been well known that performing register allocation before software pipelining may introduce unacceptable anti dependences due to the reuse of registers, which may limit software pipelining [17, 3]. On the other hand, if software pipelining is done before register allocation, more registers than necessary may be needed, which may cause unnecessary register spillings and severely degrade the performance of the pipelined loop [3] However, simultaneous register allocation and software ....

[Article contains additional citation context not shown here]

B. R. Rau, M. Lee, P.P. Tirumalai, and M.S. Schlansker. Register allocation for software pipelined loops. In proceedings of PLDI, 1992.

.... conditional code and early exits [17] 18] 19] Predicated execution can also help reduce code expansion of a modulo scheduled loop [20] A rotating register file or a technique called modulo variable expansion allows the schedules to avoid register conflicts due to the overlapping iterations [12][21]. While clustering the functional units and register file helps achieve a higher clock rate for the processor, overall modulo schedule performance will be improved only if the performance degradation due to explicit communication is small. Performance degradation may occur because of two factors: ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schansker, `Register allocation for software pipelined loops,' Proceedings of the Conference on Programming Language Design and Implementation, pp. 283-299, June 1992.

....large trip counts. Finally, the register requirements of the schedule may also impact performance if they exceed the number of available registers. In this case, the schedule is unfeasible and some actions must be taken in order to reduce the register pressure. Some possible solutions outlined in [25] and evaluated in [17] are: Reschedule the loop with an increased II. In general, increasing the II reduces the register requirements but decreases the issue rate, which has a direct negative effect on the execution time. Add spill code. This again has a negative effect since it increases ....

....to every iteration of the loop. By overlapping the lifetimes of the different iterations, a pattern of length II cycles that is indefinitely repeated is obtained. This pattern is shown in Fig. 2c. This pattern indicates the number of values that are live at any given cycle. As shown in [25], the maximum number of simultaneously live values MaxLive is an accurate approximation of the number of register required by the schedule. 2 In this section, the register requirements of a given schedule will be approximated by MaxLive. However, in the experiments section, we will measure the ....

[Article contains additional citation context not shown here]

 B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker, "Register Allocation for Software Pipelined Loops," Proc. ACM SIGPLAN '92 Conf. Programming Language Design and Implementation, pp. 283299, June 1992.

....a limited number of registers and the register allocator fails to find a solution with the number of registers available, some additional action must be taken. Different alternatives to fit the register requirements of a modulo scheduled loop in the available number of registers were outlined in [26]. One of the options, used by the Cydra 5 compiler [12] is to reschedule the loop with an increased II . If, after several trials, the compiler is unable to find a valid schedule requiring less registers than available, the compiler schedules the loop using local scheduling techniques, i.e. ....

....compact the goal is to saturate the most used resource which complicates the addition of spill load store operations without affecting the whole schedule. Cyclic interval graphs [16] can deal with lifetimes that cross loop boundaries. Other register allocation heuristics have been proposed [26, 14], that deal with lifetimes larger than the II (in the presence of hardware support) However, none of these works deal with the addition of spill code (and its scheduling) for software pipelined loops. Software pipelining and spill code has been first considered (to the best of our knowledge) in ....

[Article contains additional citation context not shown here]

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....is issued. Figure 2.d shows the register requirements for this schedule; for each cycle it shows the number of live values required by the schedule. The number of registers required can be approximated by the maximum number of simultaneously live values at any cycle, which is called MaxLive (in [22] it is shown that register allocation never requires more than MaxLive 1 registers) In Figure 2.d, MaxLive=11. Notice that with this approach, variables generated by nodes n2 and n9 have an unnecessary large lifetime due to the early placement of the corresponding operations in the schedule; as a ....

....stages. This is because SMS has been designed to optimize all: II, register requirements and stage count. Once the loops have been scheduled, a lower bound of the register requirements (MaxLive) can be found by computing the maximum number of live values at any cycle of the schedule. As shown in [22] the actual register allocation almost never requires more than MaxLive 1 registers, therefore we use MaxLive as a measurement of the register requirements. Lifetimes of loop variants start Metric SMS HRMS Top Down S II 8815 8839 10113 II MII 1.0101 1.0128 1.1588 Loops with II MII 18 31 ....

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283-299, June 1992.

....the experimental tool Ictneo [2] and software pipelined using Hypernode Reduction Modulo Scheduling [15,16] a register pressure sensitive heuristic that achieves near optimal schedules. Register allocation has been performed using the wands only strategy and the end fit with adjacency ordering [22]. When a loop requires more than the available number of registers, spill code is added and the loop is rescheduled [14] The organization of the paper is as follows: Section 2 describes the replication and widening techniques and outlines the advantages and drawbacks of both. Section 3 presents ....

B.R. Rau, M. Lee, P. Tirumalai, and P Schlansker. Register allocation for software pipelined loops. In Proc. of the PLDI-92, pp. 283-299, June 1992.

....of a variable are renamed at compile time [6] In the traditional approach, when MVE is required, the constructed schedule is unrolled a number of times. For any loop the required degree of unroll, henceforth referred to as unroll factor, is determined by the longest lifetime among the variables [12]. Because iterations are initiated every II cycles, unroll factor can be calculated as : Unroll Factor = max i lifetime i II The unrolled schedule has an II which is equal to the II of the original loop multiplied by the unroll factor. In our example, the kernel has to be unrolled d 3 2 e = ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN '92 Conf. on Programming Language Design and Implementation, pages 283--299, San Francisco, CA, June 17--19, 1992.

....is simply not available in the loop. To provide a comparison with a similarly configured single instruction stream, multiple issue architecture these loops were hand compiled for a 4 issue VLIW architecture. The VLIW architecture chosen is based upon the most sophisticated version found in [57]. This VLIW machine allows four instructions to be issued per clock cycle and there are no limitations on the type of instructions that can be issued. The register file is capable of handling eight read and four write requests on each cycle, and perfect register renaming (using a rotating register ....

....VLIW machine allows four instructions to be issued per clock cycle and there are no limitations on the type of instructions that can be issued. The register file is capable of handling eight read and four write requests on each cycle, and perfect register renaming (using a rotating register file [57]) Chapter 5: Performance of the MISC Architecture 65 Table 5.2: LLL Comparison: MIPS vs MISC 4 Benchmark MIPS MISC 4 Performance Loop (cycles) cycles) Improvement LLL1 5611 1232 4.55 LLL2 1112 256 4.34 LLL3 6664 2063 3.23 LLL4 3011 753 3.99 LLL5 6979 1994 3.50 LLL6 7726 4982 1.55 LLL7 ....

B. R. Rau, M. Lee, P. P. Tirumalai and M. S. Schlansker, Register Allocation for Software Pipelined Loops, Proceedings of the ACM SIGPLAN 1992 Conference on Programming Language Design and Implementation, (1992) 283-299.

.... Word (VLIW) and superscalar machines [1, 2, 3] Software pipelining is an efficient compilation technique to exploit ILP for loops, which initiates successive iterations before previous iterations complete [4, 5, 6, 7, 8, 9, 10, 11, 12] Register Allocation is another key compilation issue [13, 14, 15, 16, 17]. It has been wellknown that a strong interaction exists between software pipelining and register allocation. On one hand, performing register allocation before software pipelining may introduce unacceptable anti dependences due to the reuse of registers, which may limit software pipelining [17, ....

....16, 17] It has been wellknown that a strong interaction exists between software pipelining and register allocation. On one hand, performing register allocation before software pipelining may introduce unacceptable anti dependences due to the reuse of registers, which may limit software pipelining [17, 3]. On the other hand, if software pipelining is done before register allocation, more registers than This work was supported by the Lise Meitner Stipendium funded by the Austrian Science Foundation (FWF) and the Austrian Science and Research Ministry. y Email: jian mips.complang.tuwien.ac.at; ....

[Article contains additional citation context not shown here]

B. R. Rau, M. Lee, P.P. Tirumalai, and M.S. Schlansker. Register allocation for software pipelined loops. In proceedings of PLDI, 1992.

.... Very Long Instruction Word (VLIW) and superscalar machines [1, 2, 3] Software pipelining is an efficient compilation technique to exploit ILP for loops, which initiates successive iterations before previous iterations complete [4, 5, 6, 7] Register Allocation is another key compilation issue [8, 9, 10, 11]. It has been well known that register allocation may introduce anti dependences due to the re use of registers, which limit the loops ILP to be exploited by software pipelining [11, 3] The interaction between register allocation and loop free code scheduling has been studied since the mid ....

.... before previous iterations complete [4, 5, 6, 7] Register Allocation is another key compilation issue [8, 9, 10, 11] It has been well known that register allocation may introduce anti dependences due to the re use of registers, which limit the loops ILP to be exploited by software pipelining [11, 3]. The interaction between register allocation and loop free code scheduling has been studied since the mid 1980s [12, 13, 8, 14, 15] The register allocation for software pipelined loop and lifetime sensitive software pipelining approaches have been studied by some researchers and some efficient ....

[Article contains additional citation context not shown here]

B. R. Rau, M. Lee, P.P. Tirumalai, and M.S. Schlansker. Register allocation for software pipelined loops. In proceedings of PLDI, 1992.

....pipeline. As discussed later, it is possible to not have any epilogue code if the prologue code is speculatively executed [34] 35] Also, the number of stages in the prologue and epilogue may depend on the register allocation scheme. Furthermore, it is possible to have multiple epilogues [36], 37] The benefit of software pipelining can be understood by comparing the time to execute 100 iterations of the loop of Figure 3.1 before and after software pipelining. Without any overlapping, the loop in Figure 3.1(b) takes 4 cycles to execute and thus 100 iterations would take 400 cycles. ....

....With only one exit from the loop, the software pipelined loop must execute S k U times, where k is an integer greater than or equal to one. A non software pipelined version of the loop 3 The number of stages in the prologue and epilogue may depend on the register allocation scheme [36]. 80 is required to execute the remaining number of iterations. This loop is referred to as the preconditioning loop. If the loop trip count is greater than S U , the remaining number of iterations is (trip count Gamma S) mod U . If the trip count is less than S U , then only the non ....

[Article contains additional citation context not shown here]

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker, "Register allocation for software pipelined loops," in Proceedings of the ACM SIGPLAN 92 Conference on Programming Language Design and Implementation, pp. 283--299, June 1992.

.... length of all lifetimes divided by II [11] MinAvLive = 2 6 6 6 X 8u2V MinLT u =II 3 7 7 7 Once a loop has been scheduled, an absolute lower bound on the schedule s register pressure, MaxLive, can be found by computing the maximum number of values that are alive at any cycle of the schedule [16]. Let t u be the cycle where a node u has been scheduled. Then the lifetime, LT u , of a value generated by a node u is LT u = max 8v2Succ(u) t v Gamma t u ffi (u;v) Theta II And, due to the modulo constraint, MaxLive can be calculated as follows: for i = 0 to II do LifeV ector(i) 0 for ....

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....interfering with previously generated values. Register Allocation: Once a loop has been scheduled, register allocation determines its register requirements. How to allocate registers for moduloscheduled loops is beyond the scope of this paper. For an extensive discussion of the problem see [12]. The Wands Only strategy combined with the First Fit allocation schema have been chosen to allocate registers. Wands Only is the strategy that has the lowest empirical complexity, and the one that obtains the more optimal results in terms of registers. For this strategy all the allocation schemas ....

....a sack we have to solve two assignment problems: assigning values to registers and assigning values to the sack so that no conflicts occur when transferring values. The first of these problems is the traditional problem of register assignment and, for modulo scheduled loops, has been studied in [12]. In the rest of this section, we describe the algorithm we propose to assign values to the sack. A set of values can be assigned to a sack if their reservation tables are fully compatible; that is, no more than one read and one write access is allowed in a cycle. Thus, values whose reservation ....

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

....issued. Figure 2.d shows the register requirements for this scheduling; for each cycle it shows the number of live values required by the scheduling. The number of registers required can be approximated by the maximum number of simultaneously live values at any cycle, which is called MaxLive (in [20] it is shown that register allocation never requires more than MaxLive 1 registers) In Figure 2.d, MaxLive=11. Notice that with this approach, 4 variables generated by nodes n2 and n9 have an unnecessary large lifetime due to the early placement of the corresponding operations in the ....

....# Live values Figure 2: Top Down scheduling: a) Schedule of one iteration, b) Lifetimes of variables, c) Kernel of the scheduling, and d) Register requirements. 6 execution time. Otherwise, some action should be taken in order to reduce the register pressure. Some possible solutions outlined in [20] and evaluated in [2] are: Reschedule the loop with an increased II. In general, increasing the II will reduce MaxLive but it decreases the issue rate. Add spill code. This again has a negative effect since it increases the required memory bandwidth and it will result in more memory ....

[Article contains additional citation context not shown here]

B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283-299, June 1992.

....satisfy the modulo scheduling constraint. In future, we plan to compare our co scheduling method with other software pipelining methods [9, 18] 6 Related Work Resource constrained software pipelining has been studied extensively by several researchers and a number of modulo scheduling algorithms [1, 3, 4, 5, 6, 9, 11, 12, 16, 17, 18, 20, 21, 22] have been proposed in the literature. A comprehensive survey of these works is provided by Rau and Fisher in [15] As mentioned in Section 4.3, the Co Scheduling method discussed in this paper uses a variation of Huff s Slack Scheduling method [9] The work presented in this paper is unique in ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. In Proc. of the SIGPLAN '92 Conf. on Programming Language Design and Implementation, pages 283--299, San Francisco, Calif., Jun. 17--19, 1992. ACM SIGPLAN. SIGPLAN Notices, 27(7), Jul. 1992.

....50x50 case is interesting. For a matrix this small, cache performance is not a factor. We believe the performance difference comes from the way code is generated. For superscalar architectures like the HP, a code generation scheme called software pipelining is used to generate highly parallel code [27, 33]. However, software pipelining requires a lot of registers to be successful. In our code, we performed unroll and jam to improve cache performance. However, unroll and jam can significantly increase register pressure and cause software pipelining to fail [7] On our version of LU decomposition, ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. SIGPLAN Notices, 27(7):283--299, July 1992. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

....of software pipelining. The third goal of this research is to measure the benefit of using memory reuse analysis in software pipelining. In particular, since assuming all memory operations as cache misses is used by other researchers in studying register assignment for software pipelining [34] [22] 17] 16] we want to measure the decrease of register overuse attributed to assuming all memory operations are cache misses. The result of this measurement will show the significance of using memory reuse analysis with software pipelining. Chapter 4 explains the hardware reuse caused by ....

....scheduling combines the consideration of recurrence and resource constraints in scheduling. It is a heuristic based method that is practical for use in a general purpose compiler. Its scheduling, code generation and register assignment algorithms have been well studied [25] 33] 22] 35] 44] [34] [16] Several experimental evaluations have shown that the iterative modulo scheduling method can achieve near optimal performance for a large number of benchmark loops [33] 22] 16] No other heuristic based software pipelining algorithm has been shown to have a better performance than ....

[Article contains additional citation context not shown here]

B. R. Rau, M. Lee, P.P. Tirumalai, and M. S. Schlansker. Register Allocation for Software Pipelined Loops. In Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation", pages 283--229, San Francisco, CA, June 1992.

.... be easier than on general graphs [10, 12] Second, loop software pipelining [20, 16] that is necessary to exploit the instruction level parallelism, generates variable lifetimes that may span more than one iteration, enforcing software (loop unrolling [16, 7] or hardware (rotating registers file [21]) techniques to be used. These two facts have always been treated separately. Our starting point was the following question : what is the effect of loop unrolling on the interference graph Especially, how does its chromatic number evolve with loop unrolling To study this question, we have used ....

....loop is unrolled a number of times equal to the size s of the register file, and the permutation is the cyclic one : R1; R2; R3; Rs) A (naive) allocation of variables of the loop of figure 2 into a register file of size 10 is presented in figure 7. This allocation scheme is described in [21] as the Wand Only allocation scheme (only the loop steadystate is considered) For this case, only heuristics are presented in [21] for allocating variables into a rotating register file. Because this specific case of rotating register file allocation and ordinary register file allocation ....

[Article contains additional citation context not shown here]

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. SIGPLAN Notices, 27(7):283--299, July 1992. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

.... known to be easier than on general graphs [6] Second, loop software pipelining [10] that is necessary to exploit the instruction level parallelism, generates variable lifetimes that may span more than one iteration, enforcing software (loop unrolling [10, 4] or hardware (rotating registers file [13]) techniques to be used. These two facts have always been treated separately. Our starting point was the following question : what is the effect of loop unrolling on the interference graph Especially, how does its chromatic number evolve with loop unrolling To study this question, we have used ....

....structure and loop unrolling. Hence we can study the relationship more precisely. 2. 2 Rotating register file A convenient hardware feature for dealing with variables spanning more than one iteration is the concept of rotating register file, which has been implemented on the Cydra 5 architecture [13]. At each iteration, a pointer to the register file is shifted cyclically one location ahead. The addressing of the registers is performed according to this pointer. It is also possible to address a register relative to another one, hence the possibility of addressing previous instances of a ....

[Article contains additional citation context not shown here]

B.R. Rau, M. Lee, P.P. Tirumalai, and M.S. Schlansker. Register allocation for software pipelined loops. In SIGPLAN-PLDI'92, July 1992.

....50x50 case is interesting. For a matrix this small, cache performance is not a factor. We believe the performance difference comes from the way code is generated. For superscalar architectures like the HP, a code generation scheme called software pipelining is used to generate highly parallel code [24, 31]. However, software pipelining requires a lot of registers to be successful. In our code, we performed unroll and jam to improve cache performance. However, unroll and jam can significantly increase register pressure and cause software pipelining to fail [6] On our version of LU decomposition, ....

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. SIGPLAN Notices, 27(7):283--299, July 1992. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

.... Cocke, Hopkins, and Markstein 1981] This transformation is called scalar replacement and is described in detail elsewhere [Callahan, Carr, and Kennedy 1990; Callahan, Cocke, and Kennedy 1988; Carr and Kennedy 1994; Dehnert, Hsu, and Bratt 1989; Duesterwald, Gupta, and Soffa 1993; Rau 1991; Rau, Lee, Tirumalai, and Schlansker 1992]. Essentially, any consistent true or input dependence with 0 s in the outer n Gamma 1 distance vector entries is amenable to scalar replacement. Additionally, any array reference that is invariant with respect to the innermost loop may be removed by scalar replacement. 3.2 Unroll And Jam ....

Rau, B. R., Lee, M., Tirumalai, P. P., and Schlansker, M. S. 1992. Register allocation for software pipelined loops. SIGPLAN Notices 27, 7 (July), 283--299. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

....register file is quite similar in concept to vector registers. Instead of moving the pointer every cycle, it is moved once per kernel iteration, and instead of having multiple vector registers, they are pooled into one register file. The use and allocation of rotating registers is described in [17]. One version of rotating registers first appeared in the scratchpad register files of the FPS AP 120B and FPS 164 [4] 2.2 Predicated Execution The Iteration Control Register (ICR) is a rotating register file that stores boolean values called predicates. An operation is conditionally executed ....

....is to eliminate the unneeded kernel computation during the ramp up and ramp down of the software pipeline, then SC 1 and SC 0 1 do, in fact, represent the maximum prologue and epilogue length required. The prologue and epilogue lengths are, however, also dictated by the register allocation srategy [17]. 4 Conclusions Pre conditioning a modulo scheduled loop, though acceptable on processors with little instruction level parallelism, leads to significant performance degradation on processors which either are capable of issuing many operations per cycle or are deeply pipelined. In such cases, ....

Rau, B.R., Lee, M., Tirumalai, P., and Schlanskor, M.S. Register allocation for software pipelined loops. In Proceedings of the SlGPLAN'92 Conference on Programming ltnguage Design and Implementation, (San Francisco, 1992).

....[36] The schedule for the kernel may be adapted for the prologue and epilogues. Alternatively, the prologue ana epilogues can te scneculecl along wth the rest of the code surrounding the loop while honoring the constraints imposed by the schedule for the kernel. Rotating register allocation [35] (or traditional register allocation if modulo variable expansion was done) is performed for the kernel. The prologue and epilogues are treated along with the rest of the code surrounding the loop in such a way as to honor the constraints imposed by the register allocation for the kernel. o ....

Rau, B.R., Lee, M., Tirumalai, P., and Schlansker, M.S. Register allocation for software pipelined loops. In Proc. SIGPLAN'92 Conference on Programming Language Design and Implementation, (San Francisco, June 17-19 1992).

No context found.

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

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B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register Allocation for Software Pipelined Loops. SIGPLAN Notices, 27(7):283--299, July 1992. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

No context found.

B. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

No context found.

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register Allocation for Software Pipelined Loops. SIGPLAN Notices, 27(7):283--299, July 1992. Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation.

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B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

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B. R. Rau et al. Register allocation for software pipelined loops. In Proceedings of conf. on programming language design and implementation, pages 283--299, San Francisco, June 1992.

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B.R. Rau, M. Lee, P. Tirumalai, and P. Schlansker. Register allocation for software pipelined loops. In Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pages 283--299, June 1992.

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