LIN, Y. R., HWANG,C.T.,AND WU, A. 1997. Scheduling techniques for variable voltage low power design. Trans. Des. Automat. Electron. Syst. 2, 2, 81--97.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in turn, results in the need for bigger sinks and costlier heat dissipation mechanisms in order to maintain the operating temperature of the ICs in its tolerance limit. The use of multiple supply voltages for energy reduction is well researched and several works have appeared in the literature [4, 3, 5, 7]. In multiple supply voltage scheme the functional units can be operated at different supply voltages. The energy savings in this scheme is often accompanied by degradation of performance because of increase in critical path delay. The degradation in performance can be compensated using dynamic ....

Y. R. Lin, C. T. Hwang, and A. C. H. Wu. Scheduling techniques for variable voltage low power design. ACM Trans. on Design Automation of Electronic Systems, 2(2):81--97, Apr 1997.

....parallelism and or pipelining has to be incorporated [1] The resulting circuit consumes lower average power while meeting the global throughput constraint at the cost of increased circuit area. Another way of maintaining the throughput is to use resources operating at multiple voltages [2] [7]. This has the advantage of allowing modules on the critical paths to be assigned to the highest voltage levels (thus meeting the required timing constraints) while allowing modules on noncritical paths to be assigned to the lower voltages (thus reducing the power consumption) Supporting ....

....when the latency constraint is 1.5 times the critical path delay, the average reduction is 39 and when the latency constraint is two times the critical path delay, the average reduction is 58.5 . There are several scheduling algorithms for multiple voltage resources in the literature today [2] [7]. These algorithms can be classified into i) only latency constrained (i.e. latency is a hard constraint and resources are minimized) 3] 4] ii) only resource constrained (i.e. resource is a hard constraint) 5] and iii) latency and resource constrained (i.e. both latency and resource are ....

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Y.-R. Lin, C.-T. Hwang, and A. C.-H. Wu, "Scheduling techniques for variable voltage low power design," ACM Trans. Design Automation Electronic Syst., pp. 81--97, Apr. 1997.

....from 1.2V to 3.8V wi thi n 70swiC an energy e#ci ency of 0.54 5.6mW MIP. To compensate the complexi ty of real vari able voltage system, we have seen plenty of e#ortsi the followio two di ecti ns. On one hand, there have been many proposal andi mplementati n of multiC) supply voltage systems [6] [14], 20] 22] These research groups have addressed the use of two or three diH; ete supply voltages. Thei deai s to swi tch among thesesi multaneously avai lable voltages accordiH to the processiW load, computati n requi ement, latency constra i t, etc. On the other hand, i,q l var i able voltage ....

Y.R. Lin, C.T. Hwang, and A.C. Wu. Scheduling techniques for variable voltage low power designs. ACM Transactions on design Automation of Electronic Systems, Vol. 2, No. 2, pp. 81-97, 1997.

....in Table I to discuss related work. A. Dedicated hardware When crafting dedicated hardware, for example, a GSM speech codec or JPEG compressor, all possible workload details are known in advance. Therefore the optimal clock schedule can often be calculated with brute force at chip design time [14]. This can be costly since the non preemptive clock scheduling problem, where task cannot be interrupted, is NP complete [15] Hong et al. present an effective heuristic yielding schedules that are within 2 of the optimum [15] In the preemptive case the optimal schedule can be computed with an ....

Y.-R. Lin, C.-T. Hwang, and A.C.-H. Wu, "Scheduling techniques for variable voltage low-power design," ACM Trans. on Design Automation of Electronic Systems, vol. 2, no. 2, pp. 81--97, Apr 1997.

.... both general purpose computation [28] and DSP computations [11] Numerous behavioral synthesis research efforts have also addressed power minimization [23] Four research groups have addressed the use of multiple (in their software implementation restricted to two or three) different voltages [2, 13, 18, 24]. They used the term variable voltage for a fixed number of simultaneously available voltages. 3 Preliminaries 3.1 Task model AsetT of independent tasks is to be executed on a system on chip. Each task T i 2 T is associated with the following parameters: # a i its arrival time # d i its ....

Y.-R. Lin, C.-T. Hwang, and A.C.-H Wu. Scheduling techniques for variable voltage low power designs. ACM Transactions on design Automation of Electronic Systems, 2(2):81--97, 1997.

.... synthesis research efforts have also addressed power minimization; for example, see the survey of [43] Four research groups in particular have addressed the use of multiple (in their software implementation, restricted to two or three) different voltages for behavioral synthesis [7] 23] [35], 44] Interestingly, although they used the term variable voltage, they actually addressed scheduling when a fixed number of simultaneously available voltages are used. Therefore, there is no similarity between our work and these efforts beyond accidental similarity of terminology. III. ....

Y.-R. Lin, C.-T. Hwang, and A. C.-H. Wu, "Scheduling techniques for variable voltage low power designs," ACM Trans. Design Automation Electron. Syst., vol. 2, no. 2, pp. 81--97, 1997.

....of operations to clock cycles in which these operations will be executed, has to be performed. This process is called scheduling. A number of power conscious scheduling algorithms have been proposed in literature, such as (Mehra and Rabaey, 1996; Martin and Knight, 1996; Monteiro et al. 1996; Lin et al. 1997). They typically have proactive character in the sense that they try to nd a mapping of operations onto clock cycles which allows a power ecient implementation of the speci ed behavior. Since scheduling determines the maximum delay within a clock cycle, for instance, it also impacts the ....

Lin, Y.-R., Hwang, C.-T., and Wu, A. C.-H., Scheduling Techniques for Variable Voltage Low Power Designs, ACM Transactions on Design Automation of Electronic Systems, 2 , 1-22, 1997.

....when required to provide detailed workload descriptions. When crafting an application specific system, for example, a GSM speech codec or JPEG compressor, the exact workload is known in advance. Therefore the optimal clock schedule can often be calculated with brute force at chip design time [7]. This can be costly since clock scheduling is NP complete when tasks may not be preempted [5] Hong et al. present an effective heuristic yielding schedules that are within 2 of the optimum [5] In the preemptive case the optimal schedule can be computed with an O(n log 2 n) off line algorithm ....

Y.-R. Lin, C.-T. Hwang, and A.C.-H. Wu. Scheduling techniques for variable voltage low-power design. ACM Trans. on Design Automation of Electronic Systems, 2(2):81--97, Apr 1997.

....at a lower but fixed supply voltage. The tight deadline on TaskA means that supply voltage can not be lowered less than Vdd = 2:97 volts. Thus, the system operates at Vdd = 2:97 volts with P (2:97 volts) 0:67 Watts. TaskA is executed in the interval [0, 6] TaskB is executed in the interval [6,12]. The average power consumption is 0:67 Watts. Since the system can be shut down during the interval [12, 20] the average power consumption can be lowered to 0:67 Theta 12 20 = 0:40 Watts, which results in 20 power reduction, compared to the shutdown technique. With the variable voltage ....

....less than Vdd = 2:97 volts. Thus, the system operates at Vdd = 2:97 volts with P (2:97 volts) 0:67 Watts. TaskA is executed in the interval [0, 6] TaskB is executed in the interval [6,12] The average power consumption is 0:67 Watts. Since the system can be shut down during the interval [12, 20], the average power consumption can be lowered to 0:67 Theta 12 20 = 0:40 Watts, which results in 20 power reduction, compared to the shutdown technique. With the variable voltage hardware, one can schedule the two tasks such that the TaskA is executed in the interval [0, 5] at 2.97 volts with ....

[Article contains additional citation context not shown here]

Y.-R. Lin, C.-T. Hwang, and A.C.-H Wu. Scheduling techniques for variable voltage low power designs. ACM Transactions on design Automation of Electronic Systems, 2(2):81-- 97, 1997.

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LIN, Y. R., HWANG,C.T.,AND WU, A. 1997. Scheduling techniques for variable voltage low power design. Trans. Des. Automat. Electron. Syst. 2, 2, 81--97.

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Y. R. Lin, C. T. Hwang, and A. C. H. Wu, "Scheduling Techniques for Variable Voltage Low Power Design," ACM Trans. on Design Automation of Electronic Systems, 2(2), pp. 81--97, Apr 1997.

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LIN, Y. R., HWANG, C. T., AND WU, A. C. H. 1997. Scheduling Techniques for Variable Voltage Low Power Design. ACM Transactions on Design Automation of Electronic Systems 2, 2 (Apr), 81--97.

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Y. R. Lin, C. T. Hwang, and A. C. H. Wu. Scheduling techniques for variable voltage low power design. ACM Trans. on Design Automation of Electronic Systems, 2(2):81--97, Apr 1997.

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Y. R. Lin, C. T. Hwang, and A. C. H. Wu, "Scheduling Techniques for Variable Voltage Low Power Design," ACM Trans. on Design Automation of Electronic Systems, 2(2), pp. 81--97, Apr 1997.

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Y. R. Lin, C. T. Hwang, and A. C. H. Wu, "Scheduling Techniques for Variable Voltage Low Power Design," ACM Transactions on Design Automation of Electronic Systems, vol. 2, no. 2, pp. 81-97, Apr 1997.

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Y.-R. Lin, C.-T. Hwang, and A. C. Wu, "Scheduling techniques for variable voltage low power designs," ACM Trans. Design Automation Electron. Syst., vol. 2, no. 2, pp. 81--97, Apr. 1997.

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Y.-R. Lin, C.-T. Hwang, and A. C.-H. Wu, "Scheduling techniques for variable voltage low-power design," ACM Trans. Design Automation Electron. Syst., vol. 2, no. 2, pp. 81--97, Apr. 1997.

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Y. R. Lin, C. T. Hwang, and A. C. H. Wu, "Scheduling Techniques for Variable Voltage Low Power Design," ACM Trans. on Design Automation of Electronic Systems, 2(2), pp. 81--97, Apr 1997.

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Lin, Y.-R., Hwang, C.-T., and Wu, A. C.-H. Scheduling techniques for variable voltage low power designs. ACM Transactions on Design Automation of Electronic Systems 2, 2 (April 1997), 81--97.

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Y. R. Lin, C. T. Hwang, and A. C. H. Wu, "Scheduling Techniques for Variable Voltage Low Power Design," ACM Transactions on Design Automation of Electronic Systems, vol. 2, no. 2, pp. 81--97, Apr 1997.

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Y-R. Lin, C-T. Hwang, and A. C. Wu, "Scheduling Techniques for Variable Voltage Low Power Designs," ACM TODAES, 1997.

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Yann-Rue Lin, Theng-Tsung Hwang, and Allen C.-H. Wu, "Scheduling Techniques for Variable Voltage Low Power Designs, " ACM Trans. DAES, vol.2, no.2, pp.81--97, April 1997.

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Y.-R. Lin, C.-T. Hwang, and A. C.-H. Wu, "Scheduling techniques for variable voltage low power designs," ACM Transactions on Design Automation of Electronic Systems 2, pp. 81 97, April 1997.

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