T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....allowed by the state space are found in order to create a correct logic implementation [52] If the synthesis algorithm is given an incomplete state space, it cannot be guaranteed to generate logic that correctly responds to all inputs to the circuit. Orbits, presented by Myers and Rokicki in [58, 59, 53], takes a somewhat different approach. It reduces the number of regions per untimed state by using partially ordered sets (or POSETs) of events rather than linear sequences to construct the geometric regions. Instead, the algorithm generates only one geometric region for any set of firing ....

....by using partially ordered sets (or POSETs) of events rather than linear sequences to construct the geometric regions. Instead, the algorithm generates only one geometric region for any set of firing sequences that differ only in the firing order of concurrent events. This algorithm is shown in [59] to result in very few geometric regions per untimed state. This algorithm differs from the partial order approaches in that is still finds a complete state space and improvement achieved by Orbits is not dependent on the verification property. However, it is limited to specifications where the ....

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Rokicki, T. G., and Myers, C. J. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification (1994), Springer-Verlag, pp. 468--480.

....should usually be set to a very low value since optimizations could potentially reduce the gate to nothing more than a wire. After the circuit is generated, it must be back annotated with timing information from the gate library and verified to be correct which is the subject of a previous paper [23] and outside the scope of this thesis. The if statements are used to select certain sequential statements to execute depending 15 on a set of input conditions. The boolean expressions after the keyword if are the conditions that are used to control whether or not the statements after the ....

T. G. Rokicki and C. J. Myers, Automatic verificaton of timed circuits, in International Conference on Computer-Aided Verification, Springer-Verlag, 1994, pp. 468--480.

....can also be used as a starting point to formal design verification. Formal verification uses formal logic and rules of inference to deduce the correctness of a design. Formal verification is a complex problem itself and is an active area of research for both synchronous and asynchronous circuits [3, 7, 38]. While formal verification is not yet an everyday practice, there has already been significant progress in this area and there is an optimistic horizon in its future. Finally, a formal model allows synthesizing a circuit automatically. If a design can be formally specified, it can, in theory, be ....

Rokicki, T. G., and Myers, C. J. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification (1994), Springer-Verlag, pp. 468--480.

....where a continuous timer is associated with each signal transition, the timed state space is infinite. A slightly better representation would be to attach a clock to each signal transition that advances only in discrete time steps [10] This does make the state space finite, but it still explodes [36]. A BDD method has been proposed in [6] to improve discrete time memory performance, but it does not address the state explosion problem inherent in discrete time. The geometric region method, where timing information is stored as a constraint matrix representing relationships between signal ....

....but it does not address the state explosion problem inherent in discrete time. The geometric region method, where timing information is stored as a constraint matrix representing relationships between signal transition times, has been shown to be an efficient way to represent a timed state space [4, 30, 35, 36]. However, even with a region based representation, the memory required to store such a state space explicitly can be prohibitive for large designs. In many domains, implicit methods have been shown to significantly reduce memory usage [9] Since state space exploration is such a memory intensive ....

Rokicki, T. G., and Myers, C. J. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification (1994), SpringerVerlag, pp. 468--480. 53

....necessary to e#ciently find all reachable timed states. Approaches based on regions or discrete time rapidly explode. Zones can do better, but explode for highly concurrent systems. We developed POSET timing which performs analysis on partially ordered sets of events rather than linear sequences [11, 10, 3, 1]. This eliminates false causality, and it can be orders of magnitude more e#cient. The runtimes for the verification of various sizes of a stari circuit, a self timed FIFO, are shown in Figure 11. It has been shown that a region based tool, timed COSPAN, runs out of 1 GByte of memory for 3 ....

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

....Finally, even though the number of interleavings is reduced, in [10] 11] one region is still required for every firing sequence explored to reach a state. If most interleavings need to be explored, these techniques could still result in state explosion. The algorithm presented in [14] [15], 16] significantly reduces the number of regions per untimed state by using partially ordered sets (or POSETs) of events rather than linear sequences to construct the geometric regions. Using this technique, untimed states do not have an associated region for every firing sequence. Instead, the ....

....the geometric regions. Using this technique, untimed states do not have an associated region for every firing sequence. Instead, the algorithm 2 generates only one geometric region for any set of firing sequences that differ only in the firing order of concurrent events. This algorithm is shown in [15] to result in very few geometric regions per untimed state. The entire timed state space is explored, so it can be used for both verification [15] 16] and synthesis [17] However, it is limited to specifications where the firing time of an event can only be controlled by a single predecessor ....

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T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

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T. G. Rokicki and C. J. Myers, "Automatic verificaton of timed circuits," in International Conference on Computer-Aided Verification. 1994, pp. 468--480, Springer-Verlag.

....initial rule in the cyclic graph is then appended to the cut graph with an enabled event which has an index greater than any other previous event with the same action. Finally, Conflicts: D#E B#C [1,5] 2,5] 1,5] 3,5] 2,4] 2. 6] 2,6] A C B D E F A D B C Conflicts: B#C [3,7] 2,5] 10,20] [15,30] a b Figure 1. Example of a timed ER structure. the rest of the rules are added with increased indices. This process can be repeated to obtain a structure of arbitrary size. The formal details are given in [11] 2.2. Timed Configurations We define the behaviors specified by a timed ER structure ....

....a clock to each of the enabled rules that advances only in discrete time steps. It has been shown that for our class of specifications that this is equivalent to the continuous model [6, 14] This does make the state space finite, but it still explodes, especially if the delay ranges are large [15]. All of the timing analysis algorithms presented here are based on geometric regions. Geometric regions are a good way to concisely represent timing information [4, 8, 2, 14] Large numbers of discrete timed states can often be condensed into a single contiguous geometric region that contains all ....

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T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on ComputerAided Verification, pages 468--480. Springer-Verlag, 1994.

....to compute the set of satisfied rules, R s . Only rules in R s are allowed to fire and cause a transition to another state. Our timing information is represented with geometric regions, first introduced in [22, 23, 24] This approach has been shown to be efficient for timed state space exploration [25, 26, 18] and can be easily modified to analyze TEL structures without any substantial increase in synthesis time. The geometric region based timing analysis method for timed ER structures is based on keeping track of the relationships between the enabling times of a set of rules. The only change that ....

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

....bound to be assigned to the causal relationships between signals. Timing analysis is then performed by our design tool ATACS using geometric regions and partially ordered sets (POSETS) of events, which has been shown to be an efficient method for representing information about timed state spaces [3, 4, 16, 17]. We use Binary Decision Diagrams (BDDs) 7] and Multi terminal Binary Decision Diagrams [10] to efficiently represent these timed state spaces. The second stage of synthesis consists of repeatedly dividing the state graph into subregions to determine the necessary behaviors. For each signal, ....

....are not explored. The size of the timing information depends on the timing algorithm being used. One representation is to attach a clock to each signal transition that advances only in discrete time steps [8] This representation can cause state space explosion, especially for large delay ranges [17]. A BDD method has been proposed in [6] to improve discrete time memory performance, but it does not address the state explosion problem inherent in discrete time. The geometric region method, where timing information is stored as a constraint matrix representing relationships between signal ....

[Article contains additional citation context not shown here]

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

....graph Once an orbital net representation has been obtained that satisfies the single behavior place requirement, a technique called partial order timing is used to find the set of reachable states. This technique is briefly described in this subsection, but for a more complete description see [19]. Partial order timing represents sets of timed states as geometric regions, and it improves upon standard geometric timing techniques by making use of partial orders to separate concurrency from causality in the generation of these regions. Using geometric regions to represent the timed state ....

....the MMU, SIS runs out of memory during synthesis. The last two examples are compared with the 3D method showing about a 30 percent improvement in area (comparing literal count) and delay. Finally, all implementations produced by ATACS are verified to be hazard free at the gate level using orbits [19]. Table 3. Experimental results. Timed Other Design Methodologies gC ATACS SYN SIS 3D Ex. j Phij Lit Lit Area Del j Phij Area Del Area Del Lit Del SEL 53 25 27 104 5 256 160 7 158 11 n a n a SEL2 36 19 21 76 5 128 108 6.5 130 11.5 n a n a MMU 187 56 62 210 4.5 23,296 412 10 out of memory n a n a ....

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

....that can be verified. While reducing the number of interleavings is useful, in [10, 11] one region is still required for every firing sequence explored to reach a state. If most interleavings need to be explored, these techniques could still result in state explosion. The algorithm presented in [13, 14] significantly reduces the number of regions per untimed state by using partially ordered sets (or POSETs) of events rather than linear sequences to construct the geometric regions. Using this technique, untimed states do not have an associated region for every firing sequence. Instead, the ....

....the geometric regions. Using this technique, untimed states do not have an associated region for every firing sequence. Instead, the algorithm generates only one geometric region for any set of firing sequences that differ only in the firing order of concurrent events. This algorithm is shown in [14] to result in very few geometric regions per untimed state. The entire timed state space is explored, so it can be used to verify a wide range of timing properties. However, it is limited to specifications where the firing time of an event can only be controlled by a single predecessor event ....

[Article contains additional citation context not shown here]

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

....state has been seen before, the algorithm pops an unexplored timed state off the stack and continues the search. If there are no more unexplored states on the stack, the algorithm has completed. In order to reduce the state explosion problem, an algorithm based on partially ordered sets (POSETs) [13, 5] is used. The POSet al..gorithm uses partially ordered sets of events to create geometric regions rather than linear sequences. This prevents additional regions from being added for different sequences of event firings that lead to the same untimed state. POSET timing results in a compression of the ....

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

No context found.

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468--480. Springer-Verlag, 1994.

....reliable than those produced using ad hoc methods [1] The specification of timing constraints also facilitates a natural interaction between synchronous and asynchronous circuits. Our previous work introduced automatic procedures for the synthesis and verification of gate level timed circuits [2, 3, 1] and demonstrated that timed designs can be significantly smaller and faster than designs generated using other asynchronous design methodologies. The timed designs, however, are synthesized without considering explicitly the available gate library. In particular, these designs may require gates ....

T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468-- 480. Springer-Verlag, 1994.

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