A.Kondratyev M.Kishinevsky J.Cortadella L.Lavagno A.Yakovlev. Technology mapping of speed-independentcircuits: decomposition and resynthesis. In In Proc. International Symposium on Advanced Research in Asynchronous Cicuits and Systems, IEEE Computer society press, April 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....of negative gates. Two design examples show that this method minimizes the number of transistors and the switching activity, and is thus well suited for the design of basic low power library cells. 1. Introduction Speed Independent circuits are hazard free under the unbounded gate delay model [1]. Their logical behaviour is thus insensitive to the variations of gate delays that may result from temperature and process variations. This is a crucial property for designing low power library cells in submicron technologies. The correct behaviour of a delaysensitive circuit can only be ....

....or equivalently, the flow table of the circuit. But this property may be lost when logical equations and a corresponding logic diagram are derived from the flow table. It can be shown [4] that this is the case, in particular, with previously published methods based on signal transition graphs [1, 2, 3]. The method we propose also starts from a signal transition graph (STG) The key operation is to modify this STG by adding new internal variables in such a way that it gives rise to excitation functions for secondary variables which are all monotone decreasing Boolean functions, also called ....

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A. Kondratyev et al. "Technology mapping for Speed-Independent Circuits: Decomposition and Resynthesis", ASYNC'97, Eindhoven, The Netherlands, pp. 240- 253.

....of negative gates. Two design examples show that this method minimizes the number of transistors and the switching activity, and is thus well suited for the design of basic low power library cells. 1. Introduction Speed Independent circuits are hazard free under the unbounded gate delay model [1]. Their logical behaviour is thus insensitive to the variations of gate delays that may result from temperature and process variations. This is a crucial property for designing low power library cells in submicron technologies. The correct behaviour of a delaysensitive circuit can only be ....

....or equivalently, the flow table of the circuit. But this property may be lost when logical equations and a corresponding logic diagram are derived from the flow table. It can be shown [4] that this is the case, in particular, with previously published methods based on signal transition graphs [1, 2, 3]. Page 2 The method we propose also starts from a signal transition graph (STG) The key operation is to modify this STG by adding new internal variables in such a way that it gives rise to excitation functions for secondary variables which are all monotone decreasing boolean functions, also ....

[Article contains additional citation context not shown here]

A. Kondratyev et al. "Technology mapping for Speed-Independent Circuits: Decomposition and Resynthesis", ASYNC'97, Eindhoven, The Netherlands, pp. 240253.

....the circuit inputs change and consequently may unexpectedly interact with changing inputs, thereby causing hazards. Consequently, technology mapping techniques for speedindependent and timed circuits have to pay extra attention to the hazard preserving nature of their mapping techniques [1] 5] [14], 9] 21] 31] We also note that the additional challenges associated with the decomposition of input output mode circuits may partially explain why these efforts have not yet addressed optimizing for average case performance. Moreover, we believe that the ease of decomposition for ....

A. Kondratyev, M. Kishinevsky, J. Cortadella, L. Lavagno, and A. Yakovlev, "Technology mapping for speed-independent circuits: Decomposition and resynthesis," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, Apr. 1997, pp. 240--253.

.... in [4] Our original theory and algorithms provides the starting point for further extensions and improvements to both the synthesis of blocklevel implementations [21] 25] and the more recent works on the technology mapping of block level implementations into gate level realizations [12] [22]. This paper describes this underlying theory and presents algorithms for the block level synthesis algorithm the generation of a standard C implementation. We show that this synthesis problem can be solved using a binate covering algorithm. The binate covering algorithm, however, is ....

....can be optimized. Further decomposition and logic optimization is typically done to obtain improved circuits that can be mapped into given gate libraries. The decomposition and optimization techniques involved, however, are outside of the scope of this paper (for more details see, e.g. 2] 9] [22]) Important to finding the covers of region networks is the notion of a quiescent region. A maximally connected set of states in which an output signal u is not enabled is called a quiescent region of u. For each signal u in a determinate speed independent SG, there exists at most one of its ....

A. Kondratyev, M. Kishinevsky, J. Cortadella, L. Lavagno, and A. Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, April 1997.

....hazards. For this reason, traditional synthesis algorithms had to rely on the existence of virtual cell libraries which contained gates of unlimited fanin. The most recent work has focused on the sequential decomposition of memory elements (which is more powerful than combinational decomposition) [6,8,15]. Figure 2 shows an example of the decomposition of a high fanin state holding circuit element during technology mapping [6] In some cases, the decomposition is more complex in that the newly made hidden node must have additional connections, called acknowledgment wire forks, that branch off to ....

.... a high fanin state holding circuit element during technology mapping [6] In some cases, the decomposition is more complex in that the newly made hidden node must have additional connections, called acknowledgment wire forks, that branch off to other parts of the circuit to ensure hazard freedom [8,15]. Such transformations can be done at many parts of the circuit leading to many internal C elements. The key observation we make is that for the decomposition to be correct the behavior of the original signals must not be altered by the decomposition. Consequently, the original set of external ....

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. In Proc. of Intl. Symp. on Advanced Research in Asynchronous Circuits and Systems, Async-97, 1997.

....transformations of the original speci cation (e.g. by means of event insertion) to satisfy the implementability properties. It includes state assignment by solving the Complete State Coding problem [4, 5] coupled with logic minimization and speedindependent technology mapping to a target library [51, 3, 25]. Related approaches can be also found in [56, 1, 30] Methods based on the theory of state regions [12, 40, 6] provide an ecient framework for the solution of the above tasks, as they allow us to treat uniformly large sets of markings. State regions are also well suited for symbolic manipulation. ....

....de nition) In practice, these complex gates are often too large to be physically implementable as a single cell of the gate library and should be decomposed. This design step is called technology mapping and it must be performed without introducing hazards into the circuit, and was considered in [25]. It is often the case that the circuit implementing an STG has more gates than the number of signals in the initial STG speci cation. There are two reasons for this. The initial STG speci cation often de nes a behavior that can be implemented as a set of logic gates only by adding state ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, L. Lavagno M. Kishinevsky, and A. Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, April 1997.

....butaddresses mainly correctness issues. It does not describe how to use the efficient correctness checks in an optimization loop, and does not allow the sharing of a decomposed gate by differentsignal networks. The idea of combinational logic decomposition with resynthesis has beenproposed in [8, 7]. The approach combines together efficient algebraic factorization techniques used in multi level combinational logic synthesis (finding candidates for decomposition) and speed independence preserving signal insertion (the latter idea originated in [17] and was implemented efficiently in ....

.... S F and IB(F ) S F , respectively [6] ffl S 1 = S F Gamma S and S 0 = S F Gamma S Gamma . The following property states that, if there is a well formed SIP closure of the IB, then there is a minimal closure that has strictly less states than any other. Property 4. 2 [ 8] Let fb; bg be a bipartition of the SG states. Let I 1 b and let I 2 be a minimal well formed SIP set such that I 1 I 2 b. Then I 2 either does not exist or unique. In particular (the practically useful case) this property holds for I 1 = IB(b) The proof (see [8] provides a ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Technology mapping for speedindependent circuits. Technical Report TR 96-2-005, Aizu University, 1996.

....transformations of the original specification (e.g. by means of event insertion) to satisfy the implementability properties. It includes state assignment by solving the Complete State Coding problem [4, 5] coupled with logic minimization and speedindependent technology mapping to a target library [51, 3, 25]. Related approaches can be also found in [56, 1, 30] Methods based on the theory of state regions [12, 40, 6] provide an efficient framework for the solution of the above tasks, as they allow us to treat uniformly large sets of markings. State regions are also well suited for symbolic ....

....definition) In practice, these complex gates are often too large to be physically implementable as a single cell of the gate library and should be decomposed. This design step is called technology mapping and it must be performed without introducing hazards into the circuit, and was considered in [25]. It is often the case that the circuit implementing an STG has more gates than the number of signals in the initial STG specification. There are two reasons for this. ffl The initial STG specification often defines a behavior that can be implemented as a set of logic gates only by adding state ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, L. Lavagno M. Kishinevsky, and A. Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, April 1997.

....by looking at the example hazard.g taken from a set of asynchronous benchmarks. The original STG specification and its state graph are shown in Fig. 2(a) and (b) The initial implementation using the standard C architecture and its decomposition using two input gates by the method described in [7] are shown in Fig. 2(c) and (d) Our new method produces a much cheaper solution with just two D latches, shown in Fig. 2(e) Despite the apparent triviality (for an experienced human designer ) of this solution, none of the previously existing automated tools have been able to obtain it. Also ....

....states in . If a new signal is inserted using an input border, which is not well formed, then the consistency property is violated. Therefore, if an input border is not well formed, its well formed speed independent preserving closure can be constructed, as described by the algorithm presented in [7]. The insertion of a new signal can be formalized with the notion of I partition ( 19] used a similar definition) Given an SG, with a set of states , an I partition is a partition of into four blocks: and . and define the sets of states in which will have the stable value one and zero, ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev, "Technology mapping for speed-independent circuits: Decomposition and resynthesis," in Proc. 3rd Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, Apr. 1997, pp. 240--253.

....looking at the example hazard.g taken from a set of asynchronous benchmarks. The original STG speci cation and its state graph are shown in Figure 2(a) and (b) The initial implementation using the standard C architecture and its decomposition using two input gates by the method described in [7] are shown in Figure 2(c) and (d) Our new method produces a much cheaper solution with just two D latches, shown in Figure 2(e) Despite the apparent triviality (for an experienced human designer ) of this solution, none of the previously existing automated tools has been able to obtain it. Also ....

....states in IB(r) If a new signal is inserted using an input border, which is not well formed, then the consistency property is violated. Therefore, if an input border is not well formed, its well formed speed independent preserving closure is constructed, as described by an algorithm presented in [7]. The insertion of a new signal can be formalized with the notion of I partition ( 19] used a similar definition) Given an SG, A, with a set of states S, an I partition is a partition of S into four blocks: fER(x ) QR(x ) ER(x ) QR(x )g. QR(x ) and QR(x ) de ne the sets of states in which x ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, April 1997.

....the MC conditions is to make the first level (AND) gates work in a one hot fashion with acknowledgment through one of the Celements. Following this approach, various methods for speed independent decomposition and technology mapping into implementable libraries have been developed,e.g. in [14] and [7]. The former method only decomposes existing gates (e.g. a 3 input AND into two 2 input ANDs) without any further search of the implementation space. The latter method extends the decomposition to more complex (algebraic) divisors, but does not tackle the limitation inherent in the initial MC ....

....a big step in the right direction, but addresses mainly correctness issues. It does not describe how to use the efficient correctness checks in an optimization loop, and does not allow the sharing of a decomposed gate by different signal networks. The latter issues were successfully resolved in [7], but only within a standard architecture approach. In [15, 13] methods for technology mapping of fundamental mode and speed independent circuits using complex gates were presented. These methods however only identify when a set of simple logic gates can be implemented as a complex gate, but ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Technology mapping for speedindependent circuits: decomposition and resynthesis. In Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, April 1997.

....this approach, methods for speed independent decomposition into implementable libraries have beendeveloped. e.g. the method of [13] decomposes (if possible) existing gates (e.g. a 3 input AND into two 2 input ANDs) without any further search of the implementation space, and the method of [7] extends the decomposition to more complex (algebraic) divisors, but does not tackle the limitation of the initial MC architecture. This work has been funded by ESPRIT ACiD WG Nr. 214949, CICYT TIC 95 0419,EPSRC grants GR L24038 and GR K70175, and MURST (project VLSI Architectures ) The best ....

....on the implementation architecture in this work. However, as will be seen further, for the sake of practical efficiency, our implemented procedure deals only with the 2 input gates and or latches to act as G elements in the decomposition. The second important change of this work compared to [7] is that the new method is based on a full scale Booleandecomposition rather than just on algebraic factorization. This allows us to widen the scope of implementable solutions and improve on area cost (future work will tackle performanceoriented decomposition) Our second goal in generalizing the ....

[Article contains additional citation context not shown here]

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In Third International Symposium on AdvancedResearch in AsynchronousCircuits and Systems, Eindhoven, April 1997.

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A.Kondratyev M.Kishinevsky J.Cortadella L.Lavagno A.Yakovlev. Technology mapping of speed-independentcircuits: decomposition and resynthesis. In In Proc. International Symposium on Advanced Research in Asynchronous Cicuits and Systems, IEEE Computer society press, April 1997.

No context found.

A.Kondratyev M.Kishinevsky J.Cortadella L.Lavagno A.Yakovlev. Technology mapping of speed-independentcircuits: decomposition and resynthesis. In In Proc. International Symposium on Advanced Research in Asynchronous Cicuits and Systems, IEEE Computer society press, April 1997.

No context found.

A.Kondratyev M.Kishinevsky J.Cortadella L.Lavagno A.Yakovlev. Technology mapping of speed-independent circuits: decomposition and resynthesis. In In Proc. International Symposium on Advanced Research in Asynchronous Cicuits and Systems, IEEE Computer society press, April 1997.

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