O'Boyle M.F.P, Nisbet A.P., Ford R.W., A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems, PACT'96, October 1996. Home/Search Document Details and Download
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Research Proposal - O'Boyle (Correct)
....symmetrically. 4 Processors with multiple internal clusters will inevitably have to consider internal memory coherence as access times across chip start increasing beyond 20 cycles, so one obvious avenue of work is investigating whether my previous work in coherence across multiprocessors [23] can be translated into a uni processor, multi cluster setting. In order to achieve this navigation of the program and architecture design space, we need to parameterise both the machine model and code generator in a manner that describes the underlying instruction set s syntax, semantics and cost ....
O'Boyle, M.F.P., Ford, R.W., Nisbet, A.P., "A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems", IEEE PACT'96, October 1996.
On the Complexity of Loop Fusion - Darte (1999) (19 citations) (Correct)
....= S. On the other hand, if we can guarantee that each pair of dependent iterations of two consecutive parallel loops will be executed by the same processor, then we can let w(e) 0 (loops could be fused) This situation can appear in some cases when generating code with the owner computes rule [14]. 8 3.3 Loop fusion with two types and no fusion preventing edges Suppose that G = V; E = F [ F ; T ) is such that T = fS; Pg (only two types) and F is empty (no fusion preventing edges) Then, any valid optimal fusion partition leads to a total order on clusters either of the form SPSPSP: ....
M. F. P O'Boyle, A. P. Nisbet, and R. W. Ford. A compiler algorithm to reduce invalidation latency in virtual shared memory systems. In Proceedings of PACT'96, Boston, MA, October 1996. IEEE Computer Society Press.
On the Complexity of Loop Fusion - Darte (1998) (19 citations) (Correct)
....= S. On the contrary, if we can guarantee that each pair of dependent 7 iterations of two consecutive parallel loops will be executed by the same processor, then we can let w(e) 0 (loops could be fused) This situation can appear in some cases when generating code with the owner computes rule [12]. 3.3 Loop fusion with two types and no fusion preventing edges Suppose that G = V; E = F [ F ; T ) is such that T = fS; Pg (only two types) and F is empty (no fusion preventing edges) Then, any valid optimal fusion partition leads to a total order on clusters of the form SPSPSP: or PSPSP ....
M. F. P O'Boyle, A. P. Nisbet, and R. W. Ford. A compiler algorithm to reduce invalidation latency in virtual shared memory systems. In Proceedings of PACT'96, Boston, MA, October 1996. IEEE Computer Society Press. 16
Exact Distributed Invalidation - Ford, O'Boyle, Stöhr (2000) Self-citation (Ford) (Correct)
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O'Boyle M.F.P, Nisbet A.P., Ford R.W., A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems, PACT'96, October 1996.
Genetic Algorithm Optimised Compilation of Fortran for.. - Andrew Nisbet Self-citation (Nisbet) (Correct)
....shared memory through compiler optimisations to coherence protocols. A GAPS implementation of an exact analysis algorithm [6] for ownercomputes scheduling has been completed. The algorithm determines the array sections to be invalidated or made exclusive under the distributed invalidation [7] optimisation for sequential consistency. Current research is extending this algorithm to consider the more general case of non owner computes scheduling and the practical issues of coherence unit rounding of array sections. 6.4 Hardware Software Codesign For Superscalar processors Another ....
M.F.P. O'Boyle, A.P. Nisbet and R.W.E. Ford, A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems, Proceedings of Parallel Architectures and Compilation Techniques, Boston, USA, October 1996.
Fine Grain Synchronisation in VSM Architectures - Ford, Nisbet Self-citation (Ford Nisbet) (Correct)
....new coherency optimisations and their applicability. We are also developing compiler analysis and algorithms (for the MARS [4] parallel research compiler) to determine how and when to apply coherency optimisations. We have already developed the necessary compiler analysis [15] and algorithms [14] for a similar optimisation: distributed invalidation [5] We are also planning to investigate the potential for a hardware implementation of our optimisations in cache coherent hardware such as that provided by emergent SCI based architectures. ....
M.O'Boyle, R.W. Ford, and A.P. Nisbet. A compiler algorithm to reduce invalidation latency in virtual shared memory systems. In Proceedings of Parallel Architectures and Compilation Techniques, Boston, USA, October 1996.
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