M. Horowitz, P. Chow, D. Stark, R. Simoni, A. Salz, S. Przybylski, J. Hennessy, G. Gulak, A. Agarwal and J. Acken, "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache", IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October 1987, 790-799. Home/Search Document Not in Database Summary Related Articles Check |
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Netlist Processing For Custom Vlsi Via Pattern Matching - Chanak (1995) (1 citation) (Correct)
....whether a match exists assuming an initial correspondence between some part of the subcircuit and given nets and or devices in the netlist. The first approach is to perform a brute force depth first backtracking search from the Table 4 2. Fanout Statistics for Four Netlists Design MR MIPSX[10] NV5[9] EV4[8] Description Router Microprocessor Microprocessor Microprocessor Total Number of Devices 7143 43540 740716 1695691 Total Number of Nets 2867 18572 31224 662214 Average Number of Adjacent Devices per Net 7.47 7.02 7.11 7.68 Excluded Nets Vdd, GND, reset b Vdd, GND, VDD, VSS, Phi1 , ....
M. Horowitz, P. Chow, D. Stark, R. Simoni, A. Salz, S. Przybylski, J. Hennessy, G. Gulak, A. Agarwal and J. Acken, "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache", IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October 1987, 790-799.
Performance Implications of Tolerating Cache Faults - Andreas Farid (1991) (Correct)
....(MIPS 8957278 and CCR 8902536) A.T. T. Bell Laboratories, Cray Research Foundation and Digital Equipment Corporation. 2 1. Introduction Commercial and academic microprocessor architectures are increasingly incorporating caches on the processor chip itself to avoid off chip latencies [3, 6, 8, 12]. These on chip caches are currently small, but the trend is toward larger sizes to hide relatively slower off chip memory speeds; thus, these chips devote an increasing portion of their area to the memory (tags and blocks) of the cache. As cache chip area becomes large, so will the fraction of ....
Horowitz, M., Chow, P., D. Stark, R. T. Simoni, A. Salz, S. Przybylski, J. Hennessy, G. Gulak, A. Agarwal, and J. M. Acken, "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache," IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, pp. 790 - 799, October 1987.
Automatic Synthesis of Gated Clocks for Power Reduction .. - Benini, Siegel, De.. (1994) (10 citations) (Correct)
....power dissipation of 25 with an accompanying small increase of 5 in area. Finally, we explore how this technique can be extended in new directions to realize additional power savings. 2 Background 2. 1 Two phase clocking Many large VLSI circuits use a two phase non overlapping clocking scheme [13, 14, 15]. This method of clocking minimizes clock skew problems associated with a single phase scheme at the expense of higher area. With a two phase clocking scheme, timing problems can be eliminated just by increasing the clock period, because there is no bilateral constraint on the clock waveform as ....
M. Horowitz, et al., "MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache," IEEE Journal of Solid-State Circuits, no. 5, pp. 790--799, Oct. 1987.
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