K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction Stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture," In Proc. 16th Int. Symp. on Computer Architecture, pp.78-85, June 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....show that the simple VLIW machine slightly outperforms the superscalar machine, while the VLIW machine with predicating achieves a significant speedup of 1.41x over the superscalar machine. 1 Introduction Current high end microprocessors exhibit good performance through superscalar techniques [9][10] 12] A superscalar machine dynamically schedules instructions from an instruction window on a predicted control path to exploit instruction level parallelism (ILP) Speculative execution is essential for instruction scheduling so that the scheduler can exploit ILP beyond basic block ....

K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction Stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture," In Proc. 16th Int. Symp. on Computer Architecture, pp.78-85, June 1989.

.... to further enhance machine performance (Johnson provides a good overview of these machines [9] These investigations culminate in today s dynamically scheduled superscalar designs which try to isolate instruction fetch decode from instruction issue execute to allow each to run at its own pace [8, 14, 16, 20]. Multiple instruction execution occurs when the hardware issues independent instructions from a window of dynamic instructions. To maintain scalar code compatibility, all instruction scheduling is done from this window by the hardware. Out of order execution and branch prediction provide these ....

K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction stream / Multiple instruction Pipelining): A novel High-Speed Single-Processor Architecture." Proceedings of the 16th Annual International Symposium on Computer Architecture (May 1989), pp. 78-85. 13

....This work has shown that at the basic block level, pipelining and multiple instruction issuing are essentially equivalent in their abilities to exploit fine grained parallelism. Indeed, the Astronautics ZS 1 [29] and the SIMP (Single Instruction stream Multiple instruction Pipelining) processor [21] both implement multiple independent execution pipelines to exploit the advantages of both types of architectures. This previous work has not studied the interaction of fine grained parallelism strategies with coarse grained strategies, however. Consequently, the experiments presented in this ....

Kazuaki Murakami, Naohiko Irie, Morihiro Kuga, and Shinji Tomita, "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture," International Symposium on Computer Architecture, pp. 78-85, May 1989.

....file has to provide a bandwidth of at least 2I reads and I writes per cycle. The common way of providing this bandwidth is to use a multi ported register file. Whereas a few multi ported register files have been built, for example the register files for the Cydra 5 [127] the SIMP processor [101], Intel s iWarp [79] and the XIMD processor [162] centralized, multi ported register files do not appear to be a good long term solution, as its design becomes very complex for large values of I. Therefore, decentralization of the inter operation communication mechanism is essential for future ....

....effectiveness of these approaches for applications that are not amenable to static analysis techniques (to extract parallelism) is not clear. 2.4.5. The Superscalar Paradigm An alternate paradigm that was developed at the same time as the VLIW paradigm (early 80 s) was the superscalar paradigm [80, 101, 111, 116]. The superscalar paradigm attempts to bring together the good aspects of control driven specification and data driven execution, by doing datadriven execution within a window of instructions established by control driven fetching along a single flow of control. Parallelism may be extracted at ....

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K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction Stream / Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture," Proceedings of 16th Annual Symposium on Computer Architecture, pp. 78-85, 1989.

....between the register file and the functional units. In CMOS, the area required to build read ports is proportional to the square of the number of ports [12] Whereas a few multi ported register files have been built, for example the register files for the Cydra 5 [15] the SIMP processor [14], Intel s iWarp [12] and the XIMD processor [19] we feel that centralized, multi ported register files are not a good long term solution, and that alternate means need to be explored. Ideally, these alternate means should retain the elegance of the ISA visible register file (for example the easy ....

K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction Stream / Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture," Proc. 16th Annual Symp. on Computer Architecture, pp. 78-85, 1989.

....effectively by hardware means such as chaining (i.e. forwarding a result directly from a producer to a consumer without intermediate storage) Sequential execution can be augmented to exploit the irregular type of parallelism found in most non numeric applications. Superscalar processors [10, 12, 15, 18] and VLIW processors [4] do exactly this; they stay within the realm of sequential execution, but attempt to execute multiple operations every cycle. For achieving this, superscalars scan through a window of (sequential) operations every cycle and dynamically detect independent operations to be ....

K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction Stream / Multiple Instruction Pipelining) : A Novel High-Speed Single-Processor Architecture, " Proc. 16th Annual Symposium on Computer Architecture, pp. 78-85, May 1989.

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