James E. Bennett and Michael J. Flynn, "Latency tolerance for dynamic processors," Tech. Rep. CSL-TR-96-687, Stanford University, Computer Systems Laboratory, Jan- uary 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... for pointer based data structures and evaluated their algorithms for an ILP processor similar to the MIPS R10000 [19] Bennett and Flynn compared stream buffers (a form of hardwarecontrolled prefetching) hardware stride based prefetching, and victim caches for state of the art ILP processors [2]. They found that stream buffers and stride based prefetching do not have much impact on most SPEC92 programs, as these techniques stress bus bandwidth. In another study, Bennett and Flynn proposed a prediction cache that dynamically adapts between stream buffer and victim cache functionality ....

J. E. Bennett and M. J. Flynn. Latency Tolerance for Dynamic Processors. Stanford University, CSL-TR-96-687, 1996.

....the underlying stride prediction methodology must be effective for the software prefetching to perform well. Compress is an example of an application that is not amenable to stride prediction, while ijpeg and mpeg play exhibit regular data access behav ior that is amenable to stride prediction. [19] and [20] investigate hardware stride prediction for a number of common benchmarks on a dynamically scheduled processor model. That work confirms similarly poor performance for compress. Based on this work we hypothesize that scientific applications such as linpack, wave, or fft will perform well ....

James E. Bennett and Michael J. Flynn, "Latency tolerance for dynamic processors," Tech. Rep. CSL-TR-96-687, Stanford University, Computer Systems Laboratory, Jan- uary 1996.

....the underlying stride prediction methodology must be effective for the software prefetching to perform well. Compress is an example of an application that is not amenable to stride prediction, while ijpeg and mpeg play exhibit regular data access behavior that is amenable to stride prediction. [19] and [20] investigate hardware stride prediction for a number of common benchmarks on a dynamically scheduled processor model. That work confirms similarly poor performance for compress. Based on this work we hypothesize that scientific applications such as linpack, wave, or fft will perform well ....

James E. Bennett and Michael J. Flynn, "Latency tolerance for dynamic processors," Tech. Rep. CSL-TR-96-687, Stanford University, Computer Systems Laboratory, January 1996.

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