R. K. Gupta and G. De Micheli. Specification and analysis of timing constraints for embedded systems. IEEE Trans. CAD, March 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Instead, there are usually few processes where timing is critical, typically I O processes which have to satisfy external requirements. Additionally, latency path constraints, typically between inputs and outputs or along a cycle, may have to be specified to guarantee timely completion [6, 14, 15]. 4.1. Basic translation rules Our translator uses the following basic rules when mapping a Simulink block diagram into SPI elements. 1. Each Simulink block is mapped into one SPI process. Clustering is considered in section 4.3. 2. Each Simulink port is mapped into one virtual SPI process ....

R. K. Gupta and G. D. Micheli. Specification and analysis of timing constraints for embedded systems. IEEE Trans. CAD, Mar. 1997.

....on individual tasks. These timing constraints are called intermediate constraints. Both end to end and intermediate constraints are in the form of either a minimum and maximum delay between the same execution of two different tasks or a delay between consecutive executions of the same task [4, 5, 14]. As its end to end constraints, the system can have a response time constraint, input and output jitter constraints, and input and output rate constraints. A response time constraint defines a minimum and a maximum delay between the time the system gets its stimulus from its environment and the ....

Gupta, R. K., and Micheli, G. D. Specification and analysis of timing constraints for embedded systems. IEEE Trans. Computer-Aided Design 16, 3 (Mar. 1997), 240--256.

....ensure constraint satisfiability. Although we do not show it here, it should be noted that not all constraints lead to a bound on ND operation delays. In particular, relative rate constraints can often give a deterministic answer to constraint satisfiability despite the presence of ND operations [13]. We state without proof the following results that form the basis of operation level timing constraint analysis. For details and proofs the reader is referred to the references indicated. 1. Operation delay constraints are satisfiable if and only if the constraint graph is feasible and there ....

....graph is feasible and there exist no cycles with ND operations [14] A constraint graph is considered feasible if it contains no positive cycle when the delay of ND operations is assigned to zero. 2. A maximum rate constraint, r u , in G is satisfiable if m (G) Delta r Gamma1 u [13]. Note that minimum delay and maximum rate constraints are always satisfiable. 3. The lower bound m used for checking the satisfaction of maximum rate constraints, also defines the fastest rate at which an operation in the graph model can be executed by a non pipelined implementation. This ....

R. K. Gupta and G. D. Micheli, "Specification and Analysis of Timing Constraints for Embedded Systems," (submitted. available as tech. report), University of Illinois, 1995.

....High Level Description Rate analysis Process re design Hardware Software Graphical Model Figure 1: Interaction between rate analysis and synthesis in the design of an embedded system. The problem of determining execution rates has been studied in several different contexts. Gupta and De Micheli [6] have examined the problem of rate analysis in embedded systems, but they consider very limited interaction synchronization between the component processes. Further, their algorithms require the processes to be implemented only in a non pipelined manner. Rate analysis has also been studied for ....

....of the graph. This is because such inter SCC edges are not part of any cycles in the process graph, and consequently their delay does not affect any execution rates. Let us now consider the steps involved in the rate analysis of the process graph in Fig. 6. p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 [2, 6] [4, 20] 3, 10] 9, 18] 10, 20] 1, 4] 4, 10] 3, 5] 3, 6] 7,20] 5, 8] SCC 1 SCC 2 Figure 6: Process graph used in Example 4.1 For SCC 1 : For computing r l , set al..l the edge delays to their upper bounds. l = maximum mean delay cycle in SCC 1 = max ae 20 18 6 3 ; 6 20 10 ....

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R. K. Gupta, G. De Micheli, Specification and Analysis of Timing Constraints for Embedded Systems, IEEE Trans. on CAD/ICAS, Vol. 16, No. 3, pp. 240--256, 1997.

....on individual tasks. These timing constraints are called intermediate constraints. Both end to end and intermediate constraints are in the form of either a minimum and maximum delay between the same execution of two different tasks or a delay between consecutive executions of the same task [4, 5, 14]. As its end to end constraints, the system can have a response time constraint, input and output jitter constraints, and input and output rate constraints. A response time constraint defines a minimumand a maximum delay between the time the system gets its stimulus from its environment and the ....

Gupta, R. K., and Micheli, G. D. Specification and analysis of timing constraints for embedded systems. IEEE Trans. Computer-Aided Design 16, 3 (Mar. 1997), 240--256.

....in the inner most hierarchy as index 0. In Example 2.1 below, there are two relative rate constraints on the read operation relative to the two while statements. Example 2.1. Specification of rate constraints. process example (frameEN, bitEN, bit, word) in port frameEN, bitEN, bit; out port word[8]; f boolean store[8] temp; tag A; while (frameEN) f while (bitEN) f A: temp = read(bit) store[7:0] store[6:0] temp; g write word = store; g attribute constraint minrate of A = 100 cps ; attribute constraint minrate 0 of A = 1 cps ; attribute constraint minrate 1 of A = 10 cps ; ....

....as index 0. In Example 2.1 below, there are two relative rate constraints on the read operation relative to the two while statements. Example 2.1. Specification of rate constraints. process example (frameEN, bitEN, bit, word) in port frameEN, bitEN, bit; out port word[8] f boolean store[8], temp; tag A; while (frameEN) f while (bitEN) f A: temp = read(bit) store[7:0] store[6:0] temp; g write word = store; g attribute constraint minrate of A = 100 cps ; attribute constraint minrate 0 of A = 1 cps ; attribute constraint minrate 1 of A = 10 cps ; g In this example, a ....

[Article contains additional citation context not shown here]

R. K. Gupta and G. D. Micheli, "Specification and Analysis of Timing Constraints for Embedded Systems," Tech. Report DCS-UIUC-1995, University of Illinois, 1995.

....Hardware Software implementation High Level Description Critical cycles Execution rates Figure 1: Interaction between rate analysis and synthesis in the design of an embedded system. The problem of determining execution rates has been studied in several different contexts. Gupta and De Micheli [6] have examined the problem of rate analysis in embedded systems, but they consider very limited interaction synchronization between the component processes. Further, their algorithms require the processes to be implemented only in a non pipelined manner. Rate analysis has also been studied for ....

....Using the above lemma we develop the algorithm in Fig. 8 for rate analysis of a process graph with multiple SCCs. The time complexity of this algorithm is O(jV jjEj) The following example illustrates the steps involved in the rate analysis for process graphs. p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 9 [2, 6] [4, 20] 3, 10] 9, 18] 10, 20] 1, 4] 4, 10] 3, 5] 3, 6] 7,20] 5, 8] SCC 1 SCC 2 Figure 9: Process graph used in Example 4.1 Example 4.1. Consider the process graph shown in Fig. 9. The delay intervals for the edges are shown. Notice that we do not associate a delay interval with the ....

[Article contains additional citation context not shown here]

R. K. Gupta, G. De Micheli, Specification and Analysis of Timing Constraints for Embedded Systems, submitted, available as technical report, University of Illinois, 1995.

....critical tasks Rate and satisfiability analysis RADHA HW SW delay estimation HW SW partitioning Task design in a HDL Refinement and or redesign Figure 2: The proposed design methodology for embedded systems using RADHA and RATAN. mance of these portions. RATAN is based on the theory presented in [13, 22]. The other steps in Fig. 2 are as in a typical codesign methodology; however, we are currently working on showing the use of these tools capabilities in them too. 6 Conclusions and Future Work Despite the importance of the derivation problem, the state of the art unfortunately contains only a ....

Gupta, R. K., and Micheli, G. D. Specification and analysis of timing constraints for embedded systems. IEEE Trans. Computer-Aided Design 16, 3 (Mar. 1997), 240--256.

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R. K. Gupta and G. De Micheli. Specification and analysis of timing constraints for embedded systems. IEEE Trans. CAD, March 1997.

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R. K. Gupta and G. De Micheli. Specification and analysis of timing constraints for embedded systems. IEEE Trans. CAD, March 1997.

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