S. Hauck and G. Borriello. Pin Assignment for Multi-FPGA Systems. In D. A. Buell and K. L. Pocek, editors, Second Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM '93, pages 11-13, Napa Valley, California, USA, April 10-13 1994. IEEE, Inc.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Three FPGAs external to the array of processing elements are used to control the both the system clock and the datapath while providing a PCI interface to a host computer. The array has both nearest neighbor mesh connections and eight superpin connections on each side of each processing element [67]. Superpin connections enable communication between chips using a single interconnect between adjacent pins, allowing for the creation of distribution networks while minimizing the required routing resources of the processing elements. Multiple boards may be daisy chained to form larger arrays of ....

S. Hauck and G. Borriello. Pin Assignment for Multi-FPGA Systems. In D. A. Buell and K. L. Pocek, editors, Second Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM '93, pages 11-13, Napa Valley, California, USA, April 10-13 1994. IEEE, Inc.

....with success, confirming the ability of the PARTS engine to provide high bandwidth communication for real time data intensive algorithms. 2.1. 1 Superpin Buses The array not only has nearestneighbor mesh connections, but also a set of 8 superpin connections on each side of each computing element [HauBor94]. The superpin connections make it possible to go from one chip to the next using a single connection between adjacent pins. Thus it is possible to construct soft pipeline buses or token rings or other distribution networks without using many of the routing resources on the computing elements. So ....

Scott Hauck, Gaetano Borriello, Pin assignment for multi-FPGA systems, IEEE FCCM, p.11, April 10-13, 1994.

....success, confirming the ability of the PARTS engine to provide high bandwidth communication for real time data intensive algorithms. 2.1. 1 Superpin Buses The array not only has nearestneighbor mesh connections, but also a set of 8 superpin connections on each side of each computing element [HauBor94]. The superpin connections make it possible to go from one chip to the next using a single connection between adjacent pins. Thus it is possible to construct soft pipeline buses or token rings or other distribution networks without using many of the routing resources on the computing elements. ....

Scott Hauck, Gaetano Borriello, Pin assignment for multi-FPGA systems, IEEE FCCM, p.11, April 10-13, 1994.

....connection may be closer to the route s destination than the others. To handle the pin assignment problem for multi FPGA systems, we have developed a technique that reduces the routing resource usage in the system, reducing area requirements and delay, while also speeding up the mapping process [Hauck94b, Hauck94c]. With partitioning, global placement, and routing completed, it is then necessary is to place and route the individual FPGAs. For these tasks we can use one of several reasonable commercial software packages available. For Springbok we would simply need to ensure that the output of previous ....

.... can be supported [Hauck95c] On the software end of the Springbok system, we have completed work on an efficient bipartitioning algorithm [Hauck95b] as well as methods for recursively applying bipartitioning to an arbitrary topology [Hauck95c] We have also developed pin assignment software [Hauck94b, Hauck94c], which handles part of the global routing step. Conclusions As we have shown, Springbok is a novel approach to the rapid prototyping of board level designs that offers many advantages over current systems. Its flexible architecture accommodates a great range of system sizes and topologies. With ....

S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems", University of Washington, Dept. of Computer Science & Engineering Technical Report #94-04-01, 1994. 8

....pin assignment problem. Results of interconnect synthesis are presented in Section 6. Conclusions are drawn in the final section. 2 Previous Work The problem of pin assignment and inter fpga routing, in the presence of interconnection networks, has been investigated before. Hauck and Borriello [11] present a force directed pin assignment technique for multi FPGA systems with fixed routing structure. The pin assignment and placement of logic in the individual fpgas are performed simultaneously to achieve optimal routing results. Mak and Wong [12] present a optimal board level routing ....

Scott Hauck and Gaetano Borriello. "Pin Assignment for Multi-FPGA Systems". In Proc. of FPGAs for Custom Computing Machines, pages 11--13, April 1994.

....pin assignment problem. Results of interconnect synthesis are presented in Section 6. Conclusions are drawn in the final section. 2 Previous Work The problem of pin assignment and inter fpga routing, in the presence of interconnection networks, has been investigated before. Hauck and Borriello [12] present a force directed pin assignment technique for multi FPGA systems with fixed routing structure. The pin assignment and placement of logic in the individual fpgas are performed simultaneously to achieve optimal routing results. Mak and Wong [13] present a optimal board level routing ....

Scott Hauck and Gaetano Borriello. "Pin Assignment for Multi-FPGA Systems". In Proc. of FPGAs for Custom Computing Machines, pages 11--13, April 1994. 1 All models, the symbolic evaluator and the Boolean satisfier can be made available by contacting the authors

....approaches, yielding up to an 8.5 decrease in total wirelength in the system. Our algorithm works on arbitrary topologies, including those for which iterative placement approaches generate incorrect results. Complete results, along with a more thorough discussion of this topic, can be found in [2]. ....

S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems", University of Washington, Dept. of Computer Science & Engineering Technical Report #94-04-01, April 1994.

....a high level the connections between the FPGA chips. It first selects a region of output pins on the source FPGA for a given signal, and determines which (if any) routing switches or additional FPGAs the signal must pass through to get to the destination FPGA. Detailed routing and pin assignment [Kadi94, Hauck97b, Mak97, Ejnioui99] are then used to assign signals to traces on an existing multi FPGA board, or to create traces for a multi FPGA board that is to be created specifically to implement the given circuit. Because multi FPGA systems use inter chip connections to allow the circuit partitions to communicate, they ....

S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 16, No. 9, pp. 956-964, September, 1997.

....a high level the connections between the FPGA chips. It first selects a region of output pins on the source FPGA for a given signal, and determines which (if any) routing switches or additional FPGAs the signal must pass through to get to the destination FPGA. Detailed routing and pin assignment [Kadi94, Hauck97b, Mak97, Ejnioui99] are then used to assign signals to traces on an existing multi FPGA board, or to create traces for a multi FPGA board that is to be created specifically to implement the given circuit. Because multi FPGA systems use inter chip connections to allow the circuit partitions to communicate, they ....

S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 9, pp. 956964, September, 1997.

....Since our previous comparisons involved using an automatic routing tool in the congestion examples, and since these experiments yielded distances equivalent to our previous average distance measurements, it is fairly clear that routing tools can exploit our improved topologies. As described in [8], we have developed a pin assignment tool (similar to a detailed router) for inter FPGA routing, and the only impact of the improved topologies on this tool is the loss of a slight speed optimization opportunity. Partitioning tools are also easily adapted, since the locality needed for meshes is ....

S. Hauck, G. Borriello, "Pin Assignment for Multi-FPGA Systems", University of Washington, Dept. of Computer Science & Engineering Technical Report #94-04-01, April 1994.

....the congestion examples, and since these experiments yielded distances equivalent to our previous average distance measurements, it is fairly clear that routing tools can exploit our improved topologies. We have developed a pin assignment tool (similar to a detailed router) for inter FPGA routing [Hauck94b], and the only impact of the improved topologies on this tool is the loss of a slight speed optimization opportunity. Decomposition and partitioning tools are also easily adapted, since the locality needed for Mesh circuits is still the primary concern, though the number of closest neighbors is ....

S. Hauck, G. Borriello, C. Ebeling, "Pin Assignment for Multi-FPGA Systems", 1994 IEEE Workshop on FPGAs for Custom Computing Machines, 1994.

No context found.

S. Hauck and G. Boriello, "Pin Assignment for Multi-FPGA systems", Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, 1994.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC