M. H. Kipasti, C. B. Wilkerson, and J. P. Shen. Value Locality and Load Value Prediction. In 7th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 138--147, October 1996. Home/Search Document Not in Database Summary Related Articles Check |
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Techniques Utilizing Memory Reference Characteristics for Improved .. - Wong (Correct)
....continues to improve more slowly than increases in processor speed. Several microarchitecture techniques have been developed to hide or tolerate memory latency. Some of them are purely hardware based, such as lock up free caches, multithreading, and value speculation [Kroft 81, Alverson 90, Lipasti 96] These techniques can be quite successful for hiding small latencies such as those between the on chip cache (L1) and a closely integrated second level cache (L2) However, in a performance study of the Pentium Pro, Bhandarkar and Ding specifically point out that servicing L2 misses was a ....
M. H. Kipasti, C. B. Wilkerson, and J. P. Shen. Value Locality and Load Value Prediction. In 7th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 138--147, October 1996.
Branch-directed and Pointer-based Data Cache Prefetching - Liu, Dimitri, Kaeli (1999) (1 citation) (Correct)
....with tagged prefetching compared to adding pointerbased prefetching approach suggested by Luk and Mowry may overcome this problem, though we may have to add more history in order to prefetch far enough in advance. Value prediction may also be useful in order to produce the best prefetch stream [32]. We plan to pursue these questions in future work. 6 Conclusion Cache memories are commonly used to reduce the performance gap between microprocessor and memory speeds. Prefetching can be employed to increase the chances that a memory line will reside in the cache when it is requested by the ....
M.H. Lipatsi, C.B. Wilkerson, and J.P. Shen, "Value Locality and Load Value Prediction," Proceedings of the 7th Annual Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1996, pp. 138-149.
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