S. Mehrotra, "Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation," PhD thesis, Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....et al. 32] We base our processor side prefetcher on these schemes. There are many more proposals for processor side prefetching, often for irregular applications. A tiny, nonexhaustive list includes Choi et al. 8] Karlsson et al. 17] Lipasti et al. 23] Luk and Mowry [24] Mehrotra [25], Roth et al. 30] and Zhang and Torrellas [36] Many of these schemes specifically target linked data structures. Many of them rely on program information that is available to the processor, like the addresses and sizes of data structures. Often, they need compiler support. Our scheme needs ....

S. Mehrotra, "Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation," PhD thesis, Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, 1996.

....software and hardware prefetching of pointer based programs. Some of the techniques also apply to prefetching irregular array accesses. Harrison and Mehrotra add an indirect reference buffer (IRB) to the cache to perform hardware prefetching on programs with pointers and indirect array references [45, 74]. The IRB is able to prefetch regular array references as well. The IRB consists of a recurrence recognition unit and a prefetch unit that cooperate to detect recurrent address sequences and generate prefetches based upon the reference stream pattern. For linked list traversals, the IRB is a ....

Sharad Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic And Numeric Computation. PhD thesis, University of Illinois at Urbana-Champaign, Department of Computer Science, April 1996.

....in more compact and efficient storage than a method that needs to keep track of node addresses. Another idea is similar to a hardware version of [4] where memory reference recurrences are recognized, with the addition that it recognizes indirect recurrences as well as stride recurrences [10]. This method again differs from WiseNPA in that the prefetch engine does not have any explicit knowledge of the LDSs. Also, LDSs more complex than lists cannot be effectively represented by their recurrence model, while WiseNPA s generalized architecture can support LDSs of nearly any ....

....methods [8] 9] and [11] use special prefetch buffers to store prefetched data before or instead of placing it into the L1. However, a significant prefetch buffer is logically no different than adding another way to the L1, so WiseNPA prefetches directly into the L1. Methods related to [10] [12] have the problem that the next prefetch cannot be initiated until after the memory read of the previous prefetch has completed, since the next pointer value is stored in the referenced memory. Also, it has to wait for a translation lookaside buffer (TLB) read to obtain the physical ....

[Article contains additional citation context not shown here]

S. Mehrotra, "Data prefetch mechanisms for accelerating symbolic and numeric computation," Ph.D. dissertation, University of Illinois at Urbana-Champaign, 1996.

....data from this category of memory references. Stride n: These are memory reference addresses that are strictly increasing or decreasing and separated by a constant stride. It is a natural extension of the stride 1 reference pattern and has been exploited by numerous prefetching techniques [6 8, 11, 13 15]. The typical data structure that is accessed with a stride n reference pattern is the array. Linked: In a linked memory reference pattern, the data pointed to by one address is used to compute the subsequent address. In C notation, this occurs when the statement ptr = ptr next; is executed in a ....

....= ptr next; is executed in a loop. The o set will be zero only if next is the rst element of the structure pointed to by ptr. Linked lists and tree data structures are accessed with a linked memory reference pattern. A number of techniques have been proposed to prefetch linked memory references [5, 12, 15, 16]. Irregular: Memory reference patterns that do not fall into one of the previous categories are irregular. For example, we consider a triangular memory reference pattern (i.e. stride increases by a constant on each access) as irregular. Few prefetching methods are able to deal with irregular ....

[Article contains additional citation context not shown here]

S. Mehrotra, Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation. PhD thesis, University of Illinois, Urbana, IL, 1996.

....memory that has been advocated by many researchers is hardware data prefetching. Many hardware techniques have been proposed that target a specific access pattern; sequential prefetching [1, 2] stride prefetchers [3, 4, 5, 6] and prefetchers targeting pointer chasing, namely Mehrotra s technique [7], and dependence based prefetching (DBP) 8] There are also hardware techniques targeted for multiple reference patterns e.g. Markov prefetching [9] One limitation of previous work is that the workloads that have been used do not reflect current application trends and do not take into account ....

....to reduce the cache miss latency considerably for a set of numerical kernels and benchmarks [3, 5, 12] but showed less improvements for SPEC95 int [5] How it will perform for the 10 applications we study will be seen in Section 4. 2.1. 2 Mehrotra s Prefetcher Mehrotra s prefetching mechanism [7] is an extension of the previously described stride prefetcher with added logic and prefetch table space to prefetch a special case of pointer chasing. First let us define what a producer and a consumer is in pointer chasing. In the first source code in Figure 1, the value read by the load ....

[Article contains additional citation context not shown here]

S. Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation. PhD thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, 1996.

....data structures [23, 24] They manually insert instructions to create jump pointer structures and issue prefetches. In our work, the compiler automatically generates instructions to create jump pointers and issue prefetches. Other hardware approaches for prefetching linked structures include [13, 20, 29, 30]. Our analysis for identifying accesses to linked data structures is related to the work on identifying shapes in heap allocated structures, called shape analysis (e.g. see [26, 12] A main difference is that we analyze traversal sites while shape analysis analyzes creation sites to identify ....

S. Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic And Numeric Computation. PhD thesis, University of Illinois at Urbana-Champaign, Department of Computer Science, Apr. 1996.

....they exploit the fact that often the addresses referenced by loads and stores follow an arithmetic progression. By keeping track of the last e ective address and of the address stride, previously unseen addresses are speculatively predicted [1, 5, 6] In particular, Selvidge [17] and Mehrotra [10] noticed the regularity in memory streams generated by linked list accesses. A similar hardware approach is to reproduce the address generation process in hardware and to perform it in advance of other computations [15] Our approach is di erent from the one proposed by Luk and Mowry both in the ....

S. Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation. PhD thesis, University of Illinois at Urbana-Champaign, 1996.

....of a given memory reference is equal to the previous address of the same static instruction plus a constant stride. By keeping track of the last effective address and of the address stride, previously unseen addresses are speculatively predicted [9, 5, 10] In particular, Selvidge [7] and Mehrotra [14] noticed the regularity in memory streams generated by the linked lists accesses. A similar hardware approach is to reproduce the address generation process in hardware and to perform it in advance of other computations [1] The difficulty in applying such techniques is that since the hardware ....

S.Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation. PhD thesis, University of Illinois at Urbana-Champaign, 1996.

....memory accesses. A different prefetching scheme, proposed by Lee [8] is to decode ahead in the instruction stream. More recently, Baer and Chen [1] have come up with the idea of maintaining the past history of references in a table and a look ahead program counter for prefetching. Mehrotra [11] has improved upon this idea by be Data Cache Write Buffer ORL Reference Prediction Table A D D LA PC MUX INC Instruction Cache Execution Unit PC (a) Stride Predictor Hardware Branch Prediction Table match address target branch target effective address stride prev NEXT LEVEL OF MEMORY ....

S. Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computations. PhD thesis, Univ. of Illinois at Urbana-Champaign, 1996.

....found at nonsequential memory addresses. This poses problems to most spatially based prefetching techniques. Mehrotra describes a data prefetch device called the Indirect Reference Buffer (IRB) which detects pointer chasing within the pipeline, and then communicates this to the prefetch unit [26 ]. While this design will identify a variety of different types of pointer chasing, it does not address how to get far enough ahead of the pipeline to hide the long latencies associated with accessing the upper levels of the memory hierarchy. Luk and Mowry evaluate a number of compiler based ....

S. Mehrotra, Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation, PhD Thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, 1996.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC