Hwang, K., "Computer Arithmetic", Wiley & Sons 1979, p. 121  Home/Search   Document Not in Database   Summary   Related Articles   Check

....present width adaptive data word architectures (WAD) as a new datapath design technique for constructing precision adaptive energy efficient datapath circuits. Earlier studies of arithmetic have been either algorithmic (cf. 5] or have been from the perspective of synchronous circuit design (cf. [4, 17]) Clearly almost any synchronous algorithm can be trivially adapted for asynchronous design. However, asynchronous design gives us greater freedom in choosing our algorithms and therefore the ability to explore a larger design space. In this paper we present one such exploration into the design ....

Kai Hwang. Computer Arithmetic. John Wiley & Sons, 1979.

....d) More abstract representation of the actions of programs. 4. Standardization, Expandability, Portability of programs. a) No changes inside the source program if a computer is expanded by the addition of more processors. b) Standard Floating Point Number representation and Arithmetic. [ 146,23,24] c) No change inside the source programs if these programs have to run on another Parallel Computer. However the user involvement in the design and implementation of any algorithm on Parallel Computers will be crucial for the maximum exploitation of the hardware. So the programming language ....

HWANG K., "Computer Arithmetic", John Wiley & Sons, 1979

....However, it is possible to reduce the number of subsequent multiplications using a recoding of the the exponent [4, 10, 7, 6, 16] Recoding techniques (Booth recoding, bit pair recoding, etc. for sparse representations of binary numbers have been e ectively used in multiplication algorithms [3, 17]. For example, the original Booth recoding technique [1] scans the bits of the multiplier one bit at a time, and adds or subtracts the multiplicand to or from the partial product, depending on the value of the current bit and the previous bit. The modi ed versions of the Booth algorithm scan the ....

....1 and treat it as part of the input. Supported in part by RSA Data Security Inc. Redwood City, California. 1 2 Canonical Recoding A signed digit vector D of E is a sparse recoding of E using digits from the set f1; 0; 1g. The recoding is canonical if D contains no adjacent nonzero digits [13, 3, 8]. Thus a canonical signed digit vector of E is of the form D = D n 1 D n 2 D 0 ) with D i 2 f1; 0; 1g and D i D i 1 = 0 for 1 i n 1 . It can be shown that the canonical signed digit vector for E is unique if the binary expansion of E is viewed as padded with an initial zero. This ....

K. Hwang. Computer Arithmetic, Principles, Architecture, and Design. New York, NY: John Wiley & Sons, 1979. 8

....of a set of partial counts are input, the low order bit of the result appears at the serial output. The high order bits of the result appear in the parallel outputs. If another set of bits are input, the high order portion is recirculated and added to the next result through a carryselect adder [13]. Thus, on the third cycle, another result bit appears at the serial output and the high order portion is again present at the parallel output. The process can be repeated to sum 64 inputs of any bit length. The first bit of a count reaches the central controller at the end of the third cycle, ....

Hwang, K., Computer Arithmetic, John Wiley and Sons, New York, 1979.

....and C 0 by a multiplexer MUX one should check that these control block implementations support Property I and Property II within their operating environment. The other reconfiguring component, the reconfigurable adder subtractor, is implemented by an array of Controlled Add Subtract cells ([9], page 43) The complete design, which we shall call a BVHCell, may be larger than the one shown in Figure 9(b) because of the extra hardware for multiplexing, but it should have a much shorter reconfiguration time and a simpler reconfiguration controller because one only needs to reconfigure the ....

K. Hwang, Computer Arithmetic, John Wiley, 1979.

....a 0 1 2 3 D D b b 0 1 2 3 b b . Figure 7. Bit serial architecture for a singlyredundant multiplier. block 0 (i = D) block D 2 (i = D 1) block D 1 (i = D 2) block D (i = 0) all identical blocks Figure 8. Digit serial singly redundant multiplier architecture. dant, etc. The reader is referred to [12][10] for a more detailed discussion of redundant arithmetic. The architecture of a bit serial singly redundant multiplier is shown in Fig. 7 [17] The term singly arises from the fact that one input (redundant) and output operands (redundant) belong to the set f1, 0, 1g, and another input belongs ....

K. Hwang. Computer Arithmetic, Principles, architectures, and design. John Wiley, 1979.

....a 0 1 2 3 D D b b 0 1 2 3 b b . Figure 7. Bit serial architecture for a singlyredundant multiplier. block 0 (i = D) block D 2 (i = D 1) block D 1 (i = D 2) block D (i = 0) all identical blocks Figure 8. Digit serial singly redundant multiplier architecture. dant, etc. The reader is referred to [12][10] for a more detailed discussion of redundant arithmetic. The architecture of a bit serial singly redundant multiplier is shown in Fig. 7 [17] The term singly arises from the fact that one input (redundant) and output operands (redundant) belong to the set f1, 0, 1g, and another input belongs ....

K. Hwang. Computer Arithmetic, Principles, architectures, and design. John Wiley, 1979.

....the entire table of squares is stored directly. The addressing requirements of the new storage technique are also discussed. Index Terms: Multiplication, Squares, Table of squares, Read only memories, Table look up 1 Introduction The look up table approach for multiplication is well known [1]. Rather than a direct implementation, it is of advantage to use a look up table based on a single operand. This reduces memory requirements significantly. Ling [2] proposed a single operand based transform technique to realize a multiplier. Another alternative is a table of squares. In this ....

K. Hwang, Computer Arithmetic, Wiley, New York, 1979.

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Hwang, K., "Computer Arithmetic", Wiley & Sons 1979, p. 121

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Hwang, K., "Computer Arithmetic", Wiley & Sons 1979, p. 121

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K. Hwang. Computer Arithmetic, Principles, Architecture, and Design. New York, NY: John Wiley & Sons, 1979.

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Hwang, K., "Computer Arithmetic," John Wiley & Sons, 1979.

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K. Hwang, "Computer Arithmetic", Jhon Wiley, New York, 1979.

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K. Hwang. Computer Arithmetic, Principles, Architecture, and Design. New York, NY: John Wiley & Sons, 1979.

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K. Hwang. Computer Arithmetic, Principles, Architecture, and Design. New York, NY: John Wiley & Sons, 1979.

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