K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conferenceon Hardware Description Languages and their Applications, pages385 -- 402. OCRI Publications, April 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a designerfriendly, integrated verification and synthesis environment. Khordoc, Cerny, and their collaborators have used timing, and timing like, diagrams in numerous ways for hardware reasoning. They have annotated timing diagrams with sentential behavioral assertions for interface specification [52]; these diagrams generate event graphs that are used for the actual analysis. Syntactic realizability conditions have been developed for these diagrams [20] thus reducing their role as pure graphical interface tools. Their action diagrams use a hierarchy of diagrammatic notations for behavioral ....

K. Khordoc, M. Dufresne, E. Cerny, P.A. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In CHDL, pages 385--402, April 1993.

....synthesized from STD specifications can be transformed (e.g. to obtain particular optimizations or generalizations) and the transformation can be verified against the initial specification of the synthesis process. Related work. All known approaches to use timing diagrams in a formal sense ([1, 6, 12, 5]) differ from our approach in that they have built in means to specify control structures such as iteration and concatenation (sequencing) while the declarative semantics of the STD language associates with each timing diagram a constraint on the set of admissible behaviors of a component. The ....

K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conferenceon HardwareDescription Languages and their Applications, pages385 -- 402. OCRI Publications, April 1993.

....of timing diagrams annotated with various programming language constructs for This research was conducted while the author was a graduate student at Indiana University, with financial support from AT T Bell Laboratories under the PhD Fellowship Program. the behavioral specification of designs [6, 9, 10]. Algorithmic verification has been applied to requirements expressed as timing diagrams by translating the diagrams into existing formalisms such as VHDL [11] and timed automata [2] Although some of these efforts support quantitative timing constraints (those using numeric constants) none ....

K. Khordoc, M. Dufresne, E. Cerny, P. A. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Proc. of Computer Hardware Description Languages and their Applications, pages 385--402, April 1993.

....Figure 5a fires when all places in .d make a token visible. This is the standard AND causality in Petri nets. A complementary behavior, called OR causality in [18] can be described as follows: a transition fires as soon as one of the incoming places to the transition makes the token visible. In [7] the terms AND OR causality are referred as latest earliest timing relationships respectively. This is depicted in Figure 5b. Transition c occurs as soon as the first of a or b occurs. This happens within the interval min (t a g 1 , t b g 2 ) The OR behavior can be represented using ....

K. Khordoc, M. Dufresne, E. Cerny, P. A. Babkine, and A. Silburt, "Integrating Behavior and Timing in executable specifications", in Proc. CHDL, pp. 385--402, 1993.

.... and satisfiability of timing specifications given as timing diagrams in the context of interfacing components [4] Cerny and Khordoc have done similar work [5] Several researchers propose writing behavioral specifications with algebras of timing diagrams annotated with programming constructs [17, 19]. Damm, Josko, and Schlor [6] as well as Berkane, Gandrabur, and Cerny [3] have formalized timing diagram notations for use in verification. Although their syntax differs between formalizations, all timing diagrams express some common information: patterns of value changes on signals, precedence ....

K. Khordoc, M. Dufresne, E. Cerny, P.A. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Proceedings of Computer Hardware Description Languages and their Applications, pages 385--402, 1993.

....timing diagrams and our sentential logic. The third rule would be derived from the primitive rules involving circuit diagrams, timing diagrams, and sentential logic. systems for reasoning about some aspects of systems using diagrammatic representations have appeared over the past year [4] 3] [10] [14] Many systems provide formalizations of timing diagrams [3] 10] 14] and some even provide formal definitions of the interaction between timing diagrams and sentential representations [14] none of these support multiple diagrammatic representations. Another distinguishing feature of this ....

....from the primitive rules involving circuit diagrams, timing diagrams, and sentential logic. systems for reasoning about some aspects of systems using diagrammatic representations have appeared over the past year [4] 3] 10] 14] Many systems provide formalizations of timing diagrams [3] [10] [14] and some even provide formal definitions of the interaction between timing diagrams and sentential representations [14] none of these support multiple diagrammatic representations. Another distinguishing feature of this research is that the logic has been developed directly on the ....

K. Khordoc, M. Dufresne, E. Cerny, P.A. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In CHDL, pages 385--402, April 1993.

....synthesized from STD specifications can be transformed (e.g. to obtain particular optimizations or generalizations) and the transformation can be verified against the initial specification of the synthesis process. Related work. All known approaches to use timing diagrams in a formal sense ([1, 6, 12, 5]) differ from our approach in that they have built in means to specify control structures such as iteration and concatenation (sequencing) while the declarative semantics of the STD language associates with each timing diagram a constraint on the set of admissible behaviors of a component. The ....

K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conferenceon Hardware Description Languages and their Applications, pages385 -- 402. OCRI Publications, April 1993.

....yet it illustrates our point nicely: using diagrams for reasoning about circuit and value problems is advantageous. Diagrams can also play a role in the specification and verification of systems. Timing diagrams are becoming a more popular notation for expressing behavioral specifications [17] [10], presumably because people find them clearer to use than formalisms such as temporal logic. To contrast methods, we present the behavioral specification of the single pulser in three representations: second order logic, temporal logic, and timing diagrams. In each case, we want to specify that ....

....underlying system is a suitable tradeoff for greater usability. Other researchers have explored formal usage of diagrams in limited situations in hardware reasoning. Timing diagrams have received the most attention, being cited as a more natural formalism for use in place of temporal logic [17] [10]. Other systems have employed more general usage of diagrammatic representations [5] 18] 6] All of these systems formalize diagrams by translating them into known sentential logics; proofs in these systems are carried out in the sentential logic, with the diagrams serving as interface tools. ....

K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating Behavior and Timing in Executable Specifications. In Proceedings, Computer Hardware Description Languages and their Applications, pp. 385--402, April 1993.

....from Chronology Corporation [7] We could easily use another editor for input as long as it captures the appropriate semantic information present in a timing diagram. We refer readers to [3, 18, 19] for more general discussions regarding the formal semantics of timing diagram specifications and to [2, 4, 10, 12] for some specific examples. Timing Designer allows users to specify three types of timing relationships: delays, guarantees, and constraints. Delays represent a causal relationship between two edges, and guarantees specify relationships which are guaranteed to be maintained (an environment might ....

....and constraints. 4 Examples and Related Work In this section, we present several verification examples and discuss the most relevant related work. For all examples we report execution times for tdverify in CPU seconds on a DEC 3000 with 64 MB of memory. 4. 1 A simple symbolic example [0,30] [10,10] [10,10] 40,40] X,Y] M,N] A B C D Figure 1 A timing diagram with a single constraint requiring that the second edge on signal A (event A2 ) be within [0; 30] of the first edge on signal C (event C1 ) All other times are propagation delays. Figure 1 contains a simple example taken from [1] in ....

[Article contains additional citation context not shown here]

KHORDOC, K., ET AL. Integrating behavior and timing in executable specifications. In Proceedings of the Conference on Computer Hardware Description Languages and their Applications (CHDL) (Apr. 1993).

....editor for input as long as it captures the appropriate semantic information present in a timing diagram. We refer readers to [3, 23, 26] for more general discussions regarding 1 TimingDesigner, from Chronology Corporation [7] the formal semantics of timing diagram specifications and to [2, 4, 12, 15] for some specific examples. In a timing diagram three types of relationships can be specified: delays, guarantees, and constraints. 2 Delays represent a causal relationship between two edges, and guarantees specify relationships which are guaranteed to be maintained (an environment might ....

Khordoc, K., et al. Integrating behavior and timing in executable specifications. In Proceedings of the Conference on Computer Hardware Description Languages and their Applications (CHDL) (Apr. 1993).

....in hardware design frameworks is not a new idea. Various design tools and description languages have employed diagrammatic representations [5] 7] 13] and systems for reasoning about some aspects of systems using diagrammatic representations have appeared over the past year [3] 2] [10] [12] Many systems provide formalizations of timing diagrams [2] 10] 12] and some even provide formal definitions of the interaction between timing diagrams and sentential representations [12] however, none of these support multiple diagrammatic representations. The authors of [3] present a ....

.... tools and description languages have employed diagrammatic representations [5] 7] 13] and systems for reasoning about some aspects of systems using diagrammatic representations have appeared over the past year [3] 2] 10] 12] Many systems provide formalizations of timing diagrams [2] [10] [12] and some even provide formal definitions of the interaction between timing diagrams and sentential representations [12] however, none of these support multiple diagrammatic representations. The authors of [3] present a system in which a user can reason about system states using a graphical ....

K. Khordoc, M. Dufresne, E. Cerny, P.A. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In CHDL, pages 385--402, April 1993.

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K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conferenceon Hardware Description Languages and their Applications, pages385 -- 402. OCRI Publications, April 1993.

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K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conference on Hardware Description Languages and their Applications, pages 385 -- 402. OCRI Publications, April 1993.

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Karim Khordoc, Mario Dufrense, Eduard Cerny, Philippe-Andre Babkine, and Allan Silburt. Integrating behavior and timing in executable specifications. In 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93, volume A-32, pages 399--416, April 1993. 155

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Karim Khordoc, Mario Dufrense, Eduard Cerny, Philippe-Andre Babkine, and Allan Silburt. Integrating behavior and timing in executable specifications. Technical report, Universite de Montreal, Dept d'informatique et recherche operationelle, October 1992.

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K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conference on Hardware Description Languages and their Applications, pages 385 -- 402. OCRI Publications, April 1993.

No context found.

K. Khordoc, M. Dufresne, E. Cerny, P. Babkine, and A. Silburt. Integrating behavior and timing in executable specifications. In Conference on Hardware Description Languages and their Applications, pages 385 -- 402. OCRI Publications, April 1993.

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