C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288--297, Dec. 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....designer to budget enough processing power to handle worst case computational requirements and safely meet deadlines under any circumstance. Sophisticated timing analyzers can calculate safe, tight WCET bounds for tasks executing on single issue inorder pipelines with instruction and data caches [2,11,12,14,15,16,17,18,26,34,42]. However, the level of sophistication needed to safely and accurately analyze more complex architectures is formidable. Currently, there is no way to precisely specify microarchitectures with a full complement of high performance techniques (complex dynamic branch predictors, caches, deep ....

....dynamic trace. Future work includes re integrating the D cache module into the modified static timing framework. The next component, the timing analyzer, uses the control flow information and loop bounds, caching categorizations, and pipeline description (the VISA) to derive timing predictions [2,11,12,39,40]. The pipeline simulator considers the effect of structural hazards (an instruction occupying the universal function unit for multiple cycles) data hazards (a load dependent instruction stalls for at least one cycle if it immediately follows the load) branch prediction ....

[Article contains additional citation context not shown here]

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. Real-Time Systems Symposium, pp. 288--297, Dec. 1995.

....power than accesses to larger or o# chip memories. Frameworks of WCET prediction are used to ensure that deadlines of tasks can be met. While the computation of WCET in presence of instruction caches has progressed in such a way that makes it possible to obtain an accurate estimate of the WCET [1, 2, 14], there has not been much progress with the presence of data caches. The main problem when dealing with data caches is that each load store instruction may access multiple memory locations (such as those that implement array or pointer accesses) Cache locking allows some or all of the contents ....

....with an IF THEN ELSE statement that iterates a hundred times generates 2 100 possible paths. We use a common technique known as merging to make the analysis more e#cient. This basically consists of reducing the path explosion by merging paths in those cases where a path enumeration is needed [10, 14, 24]. However, this approximation trades performance for accuracy. At every merge point, the most pessimistic assumptions are made in order to have a safe estimate. In presence of caches, this generally translates to an unknown state of the cache, since the final state of the cache for each path is ....

[Article contains additional citation context not shown here]

C.A. Healey, D. Whalley, and M. Harmon. Integrating the timing analysis of pipelining and instruction caching. In 16th Real-Time Systems Symposium, pages 288--297, 1995.

....than accesses to larger or o# chip memories. Frameworks of WCET prediction are used to ensure that deadlines of tasks can be met. While the computation of WCET in the presence of instruction caches has progressed in such a way that makes it possible to obtain an accurate estimate of the WCET [1, 2, 13], there has not been much progress with the presence of data caches. The main problem when dealing with data caches is that each load store instruction may access multiple memory locations (such as those that implement array or pointer accesses) Cache locking allows some or all of the contents ....

....loop with an IFTHEN ELSE statement that iterates a hundred times generates 100 possible paths. We use a common technique known as merging to make the analysis more e#cient. This basically consists of reducing the path explosion by merging paths in those cases where a path enumeration is needed [9, 13, 23]. However, this approximation trades performance for accuracy. At every merge point, the most pessimistic assumptions are made in order to have a safe estimate. In the presence of caches, this generally translates to an unknown state of the cache, since the final state of the cache for each path ....

[Article contains additional citation context not shown here]

C. Healey, D. Whalley, and M. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of 16th Real-Time Systems Symposium (RTSS'95), pages 288--297, 1995.

....of the WCMP, and thus for the WCET as well. Frameworks of WCET prediction are used to ensure that deadlines of tasks can be met. While the computation of WCET in the presence of instruction caches has progressed in such a way that makes it possible to obtain an accurate estimate of the WCET [1, 2, 8], there has not been much # email: xavier.vera mdh.se 1 progress with the presence of data caches. The main problem when dealing with data caches is that each load store instruction may access multiple memory locations (such as those that implement array or pointer accesses) 1.1 Coyote ....

C.A. Healey, D. Whalley, and M. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of 16th RealTime Systems Symposium (RTSS'95), pages 288--297, 1995.

....real time systems relies on #######knowledge of the worst case execution time (WCET) of hard real time tasks to check if the deadline of a task can be met. A safe upper bound on the WCET of a task can be provided through static analysis, dynamic analysis or even a combination of both techniques [34, 30, 15, 41, 24, 16, 1, 22, 23, 9, 29, 38]. Regardless of the methods utilized to obtain the WCET of tasks, experiments show a wide variation between longest and shortest execution times for manyembedded applications. In [38] execution times of real world embedded tasks vary by as much as 87 relative to their measured WCET. Speci ....

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In #### ######### ####### #########, pages 288-297, December 1995.

....current status of the pipeline and the instruction cache: the worst case timing abstraction (WCTA) A program path can be analyzed by concatenating and pruning the WCTAs of its basic blocks. The prediction of pipeline performance in combination with cache prediction is discussed in [Nil95] and [Hea94]. In [Nil95] the pipeline behavior is simulated for a given code segment. It introduces the pipeline simulator compiler, which uses a description of a processor to generate a program that simulates the execution of code on this processor. The main shortcoming of this approach is that cache ....

Healy, C. A., D. B. Whalley, M. G. Harmon, Integrating the Timing Analysis of Pipelining and Instruction Caching, in Proc. IEEE Real-Time Systems Symposium, pp. 288-297, Dec. 1995.

....underutilization of system resources. To obtain accurate prediction for modem highperformance processors, the timing effect of advanced architectural features should be taken into account. For example, several groups including Zhang et al. 15] Lim et al. 11] Li et al. 10] and Healy et al. [4] had investigated the prediction techniques for pipelined processors. However, most of existing techniques assume that processors can issue at most one instruction at each cycle, thus cannot produce accurate analysis results for modem multiple issue machines such as superscalar processors. In ....

....above example, we can compute the distance bounds between two nodes as follows. Let DW and DWX be the minimum (required) and maximum (possible) distances between the issue times of nodes i and j (i order is: i . i DX i D [D,2 ,D,2 ] 32,3 , 2,3 rain max rain max rain max [D, 4 ,D, 4 ] In [32,4 ,32,4 ], 33,4 ,33,4 ] calculating [DW z,3 , Di,j ] we consider the nodes that have dependences with node j in the IDG. We classify such nodes into the following three classes according to their positions in the IDG as shown in Figure 6: 1) the nodes preceding node i (i.e. nodes p, p2, ....

[Article contains additional citation context not shown here]

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the Timing Analysis of Pipelining and Instruction Caching. In Proceedings of the 16th Real-Time Systems Symposium, pages 288 297, December 1995.

....in underutilization of system resources. To obtain accurate prediction for modern highperformance processors, the timing effect of advanced architectural features should be taken into account. For example, several groups including Zhang et al. 15] Lim et al. 11] Li et al. 10] and Healy et al.[4] had investigated the prediction techniques for pipelined processors. However, most of existing techniques assume that processors can issue at most one instruction at each cycle, thus cannot produce accurate analysis results for modern multiple issue machines such as superscalar processors. In ....

....of these differences is the candidate value from the first class. From the second class, we take E L G 7 H as in the rG G 7 H calculation. For the third class, we 2 2 1 1 1 4 1 2 2 1 4 2 1 4 1 1 2 3 4 (a) 1 1 2 2 1 2 3 4 5 6 7 [1, 19] 1, 1] 1, 17] 2, 16] 0, 0] 1 2 3 4 5 6 7 6 7 [4, 4] 5 (b) c) M1 M2 M3 M4 Z Figure 7. IDG modifications for r sut G 7 H calculation and merging operation. calculate the sums of r sut G 7 and E L 7 H where 1 =i =v . The largest of the sums is the candidate from the last class. The r G G 7 H and r sut G 7 H ....

[Article contains additional citation context not shown here]

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the Timing Analysis of Pipelining and Instruction Caching. In Proceedings of the 16th Real-Time Systems Symposium, pages 288--297, December 1995.

....constraints (i.e. deadlines) the worst case execution times (WCETs) of the tasks are estimated in advance (prior to run time) to guarantee that required timing constraints are met. Such WCETs can be predicted by existing WCET analysis tools that produce safe and accurate WCET prediction results [3, 8]. Using a WCET analysis tool, we can find the path p worst = b 1 ,b wh ,b 3 ,b 4 ,b 5 ,b wh , b 3 ,b 4 ,b 5 ,b wh ,b 3 , 2 Since we represent the fixed clock voltage transition overhead period by the number of cycles, it can vary depending on the current clock frequency. For a simpler analysis, ....

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proc. of the 16th IEEE Real-Time Systems Symposium, pages 288--297, 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon, "Integrating the Timing Analysis of Pipelining and Instruction Caching," Proceedings of the Sixteenth IEEE Real-Time Systems Symposium, pp. 288-297 (December 1995).

....the data references are unknown. In the past few years, research in the static analysis of WCET of programs has increased. Conventional methods for static analysis have been extended from unoptimized programs on simple CISC processors [7, 22, 21] to optimized programs on pipelined RISC processors [9, 17, 28] and from uncached architectures to instruction caches [3, 11, 15] However, there has been little previous work on predicting WCET for data caching. Only three previous attempts have been reported. Rawat and Nilsen [23] used a graph coloring approach to bound data caching performance. However, ....

....a data cache miss penalty could be overlapped with other stalls. However, the results in Chapter 8 indicate that any such overestimations were small when they occurred at all. The worst case loop analysis algorithm is given in Figure 6.1. The additions 36 to the previously published algorithm [9] to handle calculated references are shown in boldface. Let n be the maximum number of iterations associated with a loop. The WHILE loop terminates when the number of processed iterations reaches n 1 or no more first misses, first hits, or calculated references are encountered as misses, hits, ....

[Article contains additional citation context not shown here]

C. A. Healy, D. B. Whalley, and M. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Symposium on Real-Time Systems, pages 288--297, December 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288--297, Dec. 1995.

No context found.

Christopher A Healy, David B. Whalley, and Marion G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the 16th Real-Time Systems Symposium, pages 288--297, December 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the IEEE Real-Time Systems Symposium, Dec. 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the IEEE Real-Time Systems Symposium, Dec. 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the IEEE Real-Time Systems Symposium, Dec. 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the Timing Analysis of Pipelining and Instruction Caching. pages 288--297, December 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288--297, Dec. 1995.

No context found.

Christopher A. Healy, David B. Whalley, and Marion G. Harmon. Integrating the Timing Analysis of Pipelining and Instruction Caching. In Proceedings of the IEEE Real-Time Systems Symposium, pages 288--297, December 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. IEEE Real-Time Systems Symposium, pp. 288-297, Dec. 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288--297, Dec. 1995.

No context found.

C. A. Healey, D. Whalley, and M. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proceedings pages 288--297, 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288-297, December 1995.

No context found.

C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. Proceedings of Real-Time Systems Symposium, December 1995.

No context found.

C.A. Healy, D.B. Whalley, and M.G. Harmon, "Integrating the Timing Analysis of Pipelining and Instruction Caching," Proc. 16th IEEE Real-Time Systems Symp. (RTSS 95), IEEE CS Press, Los Alamitos, Calif., 1995, pp. 288-297.

First 50 documents  Next 50

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC