Seamless Hardware/Software Co-Verification Datasheet, Mentor Graphics Corporation, www.mentor.com/seamless/datasheets/index.html (2003).  Home/Search   Document Not in Database   Summary   Related Articles   Check

....only on instruction set level (figure 11) Register values are simulated correctly, however timing is not considered. ISS models work on a high performance in 2000 to 20,000 instructions per second. They are commonly used for software simulation. Figure 11: Instruction Set Accurate Processor Model [13] A Survey of HW SW Cosimulation Techniques and Tools E l e c t r o n i c S y s t e m s D e s i g n L a b o r a t o r y 21 b) Techniques requiring no processor model: Instead of using models of the target processor the designer may choose other techniques to glue SW and HW components. This can ....

....phase to take new developments into account. A timing evaluation is impossible with these techniques. Often used mechanisms are: 1. The model free synchronized handshake: also called host code execution (HCE) Together with ISS models this technique is often supported by cosimulation tools [13,19]. The SW, supposed to run on the target machine, is compiled to the host workstation. The advantage is the increasing performance, which is dependent only on the HW simulation since the SW is executed at workstation speed. Communication between SW and HW is performed by a synchronized handshake ....

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Seamless Co-Verification Environment User's and Reference Manual, V 2.2, Mentor Graphics Corporation, Wilsonville, Oregon, 1996-98.

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Seamless Hardware/Software Co-Verification Datasheet, Mentor Graphics Corporation, www.mentor.com/seamless/datasheets/index.html (2003).

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