R. Morgan, Building an Optimizing Compiler, Digital Press, 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....functionality and the e#cient algorithms developed at Rice. This document describes how to use the SSA library, but it is meant neither as an introduction to SSAbased optimization nor as a detailed rationale for the Rice approach. Any of several recent compiler textbooks can provide the former [1, 4, 5]. For the latter, read the Rice paper [2] and the Rice code description [3] In the sections that follow, we point out connections between our implementation and theirs, and we also identify things that we ve done di#erently. Section 2 establishes a vocabulary. Section 3 is an introduction to ....

....to record the new definition and record all uses to record the new use occurrences. 4 Excerpts from An Example Pass An SSA based optimization pass called dcessa is distributed with Machine SUIF. This is an implementation of the dead code elimination algorithm given in Robert Morgan s textbook [4]. Without going into the details of the algorithm, we ll show how it makes use of the SSA library. The conversion of an optimization unit s CFG to SSA form is carried out by these lines: #Convert to semi pruned SSA form 5## using namespace ssa; unit ssa = new ssa cfg(unit cfg, cur unit, ....

Robert Morgan. Building an Optimizing Compiler. Digital Press, 1998.

....with the raising of an exception. We provide functions for creating and recognizing exceptional edges in a CFG. Though unusual, exceptional edges are at least possible control paths. On the other hand, there are important analysis techniques that insert completely impossible edges in the CFG [5]. They may require that every node lies on a path to the exit node, for example. To handle an infinite loop, they insert an impossible edge from one of the loop nodes to the exit. We also provide functions to create and recognize impossible edges. When the CFG is constructed, impossible edges are ....

....jumps(cfg) eliminates jumps to jumps. You should know that remove unreachable nodes renumbers the CFG, so it could invalidate node numbers that you may have saved. 5.4. 8 Reverse Postorder Node Enumeration Class CfgNodeListRpo gives you a way to enumerate the nodes of a CFG in reverse postorder [5]. Construct an instance of this class, passing a Cfg object and an optional flag indicating whether to view the graph in the normal forward direction or in reverse. The methods of CfgNodeListRpo for scanning the nodes are the same as the corresponding sequence functions. For instance, here s a ....

Robert Morgan. Building an Optimizing Compiler. Digital Press, 1998.

.... In this paper we focus on global register allocation, one of the most important transformations in a modern optimizing compiler [10] page 92) For RISC machines, Chaitin style graph coloring [6] is the dominant approach, as witnessed by its prominence in modern compiler construction textbooks [1, 16, 17]. It gives high quality allocations, runs fast in practice, and is supported by a large body of research work (e.g. 5, 8] Unfortunately, the algorithm assumes a regular register architecture consisting of a single, homogenous set of generalpurpose registers. We propose a generalization of ....

R. Morgan. Building an Optimizing Compiler. Digital Press, 1998.

....with the raising of an exception. We provide functions for creating and recognizing exceptional edges in a CFG. Though unusual, exceptional edges are at least possible control paths. On the other hand, there are important analysis techniques that insert completely impossible edges in the CFG [3]. They may require that every node lies on a path to the exit node, for example. To handle an infinite loop, they insert an impossible edge from one of the loop nodes to the exit. We also provide functions to create and recognize impossible edges. When the CFG is constructed, impossible edges are ....

....Otherwise you specialize it to perform whatever task is needed. The utility in the next section is implemented using a DepthFirstWalkAction that accumulates a list of nodes in reverse postorder. 6.1. 2 Reverse postorder sequence The following class presents the nodes of a CFG in reverse postorder [3]. CfgNodeListRpo 16c## (18c) class CfgNodeListRpo public: CfgNodeListRpo(Cfg graph, bool forward = true) virtual CfgNodeListRpo( int size( CfgNodeHandle start( CfgNodeHandle end( void prepend(CfgNode ) void append(CfgNode ) void replace(CfgNodeHandle, CfgNode ) void ....

Robert Morgan. Building an Optimizing Compiler. Digital Press, 1998.

....two consecutive statements x : y and z : x. A ow dependence exists between these statements because the second statement depends on the de nition of x in the rst. An anti dependence exists between two components A and B if exchanging A and B would result in the creation of a ow dependence [7, 28, 29]. The two consecutive statements z : x and x : y exhibits an anti dependence. An output dependence exists between two components A and B if both A and B contain a de nition of the same variable [7, 28, 29] An example of an output WHILE 0 stmtWhile Statement 0 Statement 1 WHILE 1 ....

....A and B if exchanging A and B would result in the creation of a ow dependence [7, 28, 29] The two consecutive statements z : x and x : y exhibits an anti dependence. An output dependence exists between two components A and B if both A and B contain a de nition of the same variable [7, 28, 29]. An example of an output WHILE 0 stmtWhile Statement 0 Statement 1 WHILE 1 stmtWhile Statement 2 Statement 3 Body Expression Context Context Next Next Expression Body Next Context Context Context Context Next Statement 0 WHILE 1 WHILE 0 Statement 1 Statement 3 ....

Robert Morgan. Building an Optimizing Compiler. Butterworth-Heinemann, Woburn, MA, United States of Armerica, 1998.

....reads and manipulates previously compiled code. The control flow graph (cfg)isafundamental data structure needed by almost allthetechniques that compilers use to find opportunities for optimization and to prove the safety of those optimizations. Such analysis includes global data flow analysis [17, 16], the construction of an ssa graph [8] and data dependence analysis [15, 12] Other techniques use the cfg to guide a more local analysis and replacement phase [22, 6, 19] These techniques all assume the existence of a cfg. If the source code for the transformation is compiled, scheduled code, ....

....the same label (i.e. the block has multiple predecessors in the cfg) the compiler must handle the e#ects of multiple sets of pending branches. Each of these pending branches can terminate a block and add one or more edges to the cfg.Thesee#ects cause the classic algorithms for cfg construction [1, 16, 17] to fail building a cfg that does not correctly reflect the potential flow of control in the code. Sorting out all of these e#ects adds significant complication to the cfg constructor. In a more traditional setting, the compiler writer can avoid these problems. Careful design of the ....

Charles R. Morgan. Building an Optimizing Compiler.Digital Press, 1998.

....###### ######### ############ ############### ###### Fig. 2. Compiler architecture architecture is using vertical compositionality for decomposing compilations into a sequence of simpler steps each of which can be dealt with by appropriate methods and tools, cf. Fig. 2 and e.g. [55, 40]. Actually, the first row of Fig. 2 shows a decomposition of a compiler into modules only, not necessarily into sequential steps; however, locally for each element of an intermediate representation the phases follow each other sequentially from left to right. 6 Conceptually it is thus justified ....

C. Robert Morgan. Building an Optimizing Compiler. Digital Press, Februar 1998. ISBN 155558179X.

....a SSA form is performed in multiple steps and is based on dominator information from the Control Flow Graph . We have used an algorithm created by Tarjan and Lengauer s for calculating the dominator tree [LT79] and apply an algorithm of Cytron [CFR 91] for calculating domination frontiers [Mor98] Cytron s paper also describes the SSA speci c steps, e.g. insertion of functions and renaming variables. The graph related steps are based on well known methods, and should not create any major problems. The remaining steps, involving insertion of functions and renaming variables is a bit ....

....variables used as actual parameters might a ect ow. We tested this nave approach and noticed that the overestimation was unacceptably high. Instead we implemented mappings between all formal and actual parameters which we can use to get a tight analysis. 5 Static Single Assignment form Morgan [Mor98] P graphs were transformed [ into the Static Single Assignment form of the ow graph, one of the current ow graph structures of choice for compiler development . 3.1 Introduction A program is said to be in Static Single Assignment Form if each variable gets assigned a value at ....

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R. Morgan. Building an Optimizing Compiler. Digital_Press, 1998.

....shows the relationships between instances of a variable in SSA form. Every variable gives rise to a di erent IRgraph. Each instance V i of a variable becomes a node in the IR graph; for each These are placed on edges for the purposes of this proof, to avoid the critical edge problem cited by [6, 20]. The IR graph is only used for the purposes of this proof; it is not used by our algorithm. function V i (V x1 ; V x2 ; V xk ) we add k edges to the IR graph: V xk V i Not all instances are de ned in terms of functions. We call de nitions that do not correspond ....

R. Morgan. Building an Optimizing Compiler, Digital Press, 1998.

....write. The variable referenced in an expression is not always apparent. A pointer dereference, for example, can refer to any variable whose address is known to the program. ViC uses a special variable to refer to global addressable memory. An optimizer prepass does simple alias analysis [ASU86, Mor98] locating any variables whose address is evaluated with , as well as global and static variables. The compiler identifies 89 0 1 2 3 4 5 7 6 8 9 10 11 12 13 Figure 6.5: Dataflow Graph. Edges show the data dependencies in the basic block of Figure 6.4. Statement numbers label the ....

Robert Morgan. Building an Optimizing Compiler. Digital Press, Woburn, MA, 1998.

....been replaced. This can lead to cache hits even for the first reference in a PrS. This propagation of definitions is referred to as the Line Definition Propagation of a program segment LDP[PrS] From here on, we utilize well established work in global flow analysis as known from compiler design [2, 12] for computation. 4.1. Cache Line Content Prediction In figure 3, the mapping of the program to three cache lines CL of the instruction cache according to [11] can be seen. Path analysis has found four PrS where cache behavior can be simulated while the control flow from PrS 1;3 to PrS 4;5 and ....

....Complexity can be a problem in data flow analysis, but due to the path recognition that gives an exact sequence for local definitions most cache state transitions are computed on a local level and do not add to global complexity. Compact data structures and algorithms from well established work [2, 12] are used. 4.3. Global Execution Time Computation Cache hits and misses lead to a modified execution time t i of the PrS consisting of the execution time for cache hits and misses t i = t i;hit t i;miss . The model in [11] is adapted to use PrS instead of basic blocks. Deviating from [11] our ....

R. Morgan. Building an Optimizing Compiler. Butterworth-- Heinemann, 1998.

....will definitely lead to a cache miss. In [11, 12, 13] the cache analysers are generated from a specification language working on a:out and source code. 3 AUTOMATIC PATH RECOGNITION 16 Use Define Chains for Data Access Addresses Another group is using data flow analysis and use define chains [2, 28, 27] for data cache analysis described in [9] and extended in [22] Their main assumption is that not all data accesses with complex expressions for the address have to be treated as cache misses. Use define chains for access addresses to determine whether these expressions are just depending on ....

R. Morgan. Building an Optimizing Compiler. Butterworth--Heinemann, 1998.

....on the leftedge greedy interval coloring algorithm [5] extended to a larger region of code called the tree region. 3.2.1. Tree Regions The CFG of pseudo SPARC code is partitioned into tree regions which are single entry, multiple exit subgraphs shaped like trees (same as extended basic blocks [6]) Tree regions start at the beginning of the program or at control join points and end at the end of the program or at other join points. For example, the following CFG, composed of three basic blocks (A,B,C) includes two tree regions: one region starts at label A: and ends at the flow graph ....

....edge and update h[y] i4) In this way, when the loop entry is re encountered through the back edge, we do not have to update the previous h of the region nor reallocate the region. The reconciling problem, in fact, is similar to replacing SSA OE nodes by a set of equivalent move operations [6] and we can use the same solution to minimize copies. 3.2.4. Register Spill When no free registers are available at some instruction I during the forward sweep, we heuristically choose a real register r to spill. Let us assume that r is mapped only to pseudo registers x and y at that point ....

R. Morgan, Building an Optimizing Compiler, Digital Press, 1998.

....as, for instance, when moving a method argument or return value to or from a fixed register. Copies are also required for all the inputs of a phi node, since the input values of the phi node may not be assigned to the same register as the phi node itself. In addition, we use the LIMIT algorithm [27] to split the live ranges of values around loops in which they are not referenced. The live range of a value is split by inserting copies of the value before and after the loop, which facilitate their spill of the value in deference to values which are used in those loops. The next phase is value ....

R. Morgan. Building an Optimizing Compiler. ButterworthHeinemann, Woburn, Massachusetts, 1998.

....and this paper generalizes such approaches to irreducible graphs. Our problem reduction strategy utilizes loop nesting forests, a data structure that represents the loops in a controlflow graph and the containment relation between them. The concept of loops is widely used in optimizing compilers [11]. However, while there is a well accepted notion of what the loops in a reducible graph are [19] there is less agreement about how the loop nesting forest should be defined for arbitrary graphs. For instance, Steensgaard [18] Sreedhar et al. 17] and Havlak [9] each provide a different ....

....Havlak loop nesting forest, the whole algorithm runs in almost linear time. The construction of the loop nesting forest runs in almost linear time, and the subsequent steps run in linear time. 6 Related Work Loops play a fundamental role in several loop optimizations and transformations [11]. The classical algorithm for identifying loops is Tarjan s interval finding algorithm [19] which is restricted to reducible graphs. Recently, several algorithms have been proposed for identifying loops in arbitrary graphs. This includes the algorithms described by Steensgaard [18] Sreedhar et. ....

Robert Morgan. Building an Optimizing Compiler. Butterworth-Heinemann, Woburn, MA, 1998.

....and this paper generalizes such approaches to irreducible graphs. Our problem reduction strategy utilizes loop nesting forests, a data structure that represents the loops in a controlflow graph and the containment relation between them. The concept of loops is widely used in optimizing compilers [12]. However, while there is a well accepted notion of what the loops in a reducible graph are [21] there is less agreement about how the loop nesting forest should be defined for arbitrary graphs. For instance, Steensgaard [20] Sreedhar et al. 19] and Havlak [10] each provide a different ....

Robert Morgan. Building an Optimizing Compiler. Butterworth-Heinemann, Woburn, MA, 1998.

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R. Morgan, Building an Optimizing Compiler, Digital Press, 1998.

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Morgan, R., Building an Optimizing Compiler, Butterworth-Heinemann, Boston, 1998.

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R. Morgan, Building an Optimizing Compiler, Butterworth-Heinemann, Boston, Mass., 1998.

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Morgan, R. (1998). Building an Optimizing Compiler. Boston: ButterworthHeinemann Publishers.

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Morgan, R. (1998). Building an Optimizing Compiler. Woburn, Massachusetts: Butterworth-Heinemann.

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Robert Morgan. Building an Optimizing Compiler. Digital Press, 1998.

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R. Morgan, Building an Optimizing Compiler, Butterworth-Heinemann, Boston, Massachusetts (1998).

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Robert Morgan. Building an Optimizing Compiler. Digital Press, 1998.

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Robert Morgan. Building an Optimizing Compiler. Digital Press, 1998.

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