B. Jacob and T. Mudge. (1998). Virtual Memory in Contemporary Microprocessors. IEEE Micro, Vol 18(4), pp. 60-75. Home/Search Document Details and Download
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Characterizing the d-TLB Behavior of SPEC CPU2000 Benchmarks - Kandiraju, Sivasubramaniam (2002) (Correct)
....It is only recently [28, 25, 3, 20] that the issue of prefetching TLB entries to hide all or some of the miss costs has started drawing interest. Many research findings on TLBs have also made their way into commercial offerings. A very nice survey of several of these TLB structures can be found in [15]. In all, a good deal of research has been undertaken on TLB design and evaluation. However, to our knowledge, there has not been any study looking at characterizing the TLB support that is required from an application s perspective. At the same time, different studies have used different ....
....The experimental set up is detailed in Section 3, and the results from the characterization are presented in Section 4. Section 5 summarizes the lessons learnt from this study and outlines suggestions for future TLB design and optimization. 2. RELATED WORK As was mentioned earlier, many studies [7, 15, 1, 14, 27] have pointed out the importance of the TLB and the necessity of speeding up the miss handling process. Several studies [31, 15, 23] have looked at hardware TLB structures organization and their impact on system performance in terms of capacity and or associativity. While some of these have ....
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B. Jacob and T. Mudge. Virtual Memory in Contemporary Microprocessors. IEEE Micro, pages 60--75, July-August 1998.
Main-Memory Index Structures with Fixed-Size Partial Keys - Bohannon, McIlroy, Rastogi (2001) (5 citations) (Correct)
....caches translations between virtual and physical addresses. While TLB misses are shown in [5] to have a significant effect on performance, we do not focus on TLB issues in this paper. One justification for this approach is the fact that almost all modern TLBs are capable of using superpages [14], essentially allowing single TLB entries to point to much larger regions. While posing difficulties for operating system implementors [27] this facility may effectively remove the TLB miss issue for main memory databases by allowing the entire database to effectively share one or two TLB ....
B. Jacob and T. Mudge. Virtual memory in contemporary microprocessors. IEEE Micro, 18(4), July 1998.
Virtual Memory In A 64-Bit Microkernel - Elphinstone (1999) (1 citation) (Correct)
....to the application programmer. Portions of programs can also be transparently moved to disk, which frees physical memory for other programs, and also allows a single program to use more memory than is physically available. Modern virtual memory is typically implemented by paging [Mil90, JM98b] A paged virtual memory system divides both the virtual and physical address spaces into equal sized blocks of memory. The blocks are usually termed pages in the virtual space, and frames in the physical space. Virtual memory accesses to pages are translated to physical memory accesses to ....
....structures have been intensively studied resulting in a variety of implementations. Smith provided a bibliography on early paging related research [Smi78a] Milenkovic provides a good survey of microprocessor memory management in the late 1980s [Mil90] Jacob provides a more recent survey [JM98b] TLBs are not the focus of the thesis so I do not describe them further. The following sections survey the major page table designs. For each page table, the basic structure and translation mechanism is described. The translation section is described assuming the absence of a TLB for ....
Bruce L. Jacob and Trevor N. Mudge. Virtual memory in contemporary microprocessors. IEEE Micro, 18(4), July/August 1998.
Hot Pages: Software Caching for Raw Microprocessors - Moritz, Frank, Lee.. (1999) (10 citations) (Correct)
....memory accesses so that the right entry is accessed without runtime intervention. The page table organization used for translation in Hot Pages is similar to those used in virtual memory systems in contemporary microprocessors. A survey of six commercial memory management designs can be found in [10]. There is a large body of research related to hardware solutions for caching. Our work has been mostly influenced by research where compile time and runtime software mechanisms were used to improve the performance. Hot Pages predictable scheme 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Syntetic ....
B. Jacob and T. Mudge. Virtual Memory in Contemporary Microprocessors. IEEE Micro, Aug. 1998.
Two-Level Address Storage and Address Prediction - Morancho, Llaberia, Olive (1999) (Correct)
....of the computed address and searches them in the HAT. The hash function used depends on the number of HAT entries. Fully associative lookups are possible using a HAT with a small number of entries; as a reference, current microprocessors perform fully associative lookups in up to 96 entry TLB s [12]. To reduce the eviction from HAT of useful information on a HAT miss, the 2LAP searches HAT entries that are related to zero LAT entries (empty HAT entries) To detect them, we will associate to every HAT entry a link counter that reflects the number of LAT entries linked to it. If none empty ....
B. Jacob and T. Mudge. (1998). Virtual Memory in Contemporary Microprocessors. IEEE Micro, Vol 18(4), pp. 60-75.
Hot Pages: Software Caching for Raw Microprocessors - Csaba Andras Moritz (1999) (10 citations) (Correct)
....memory accesses so that the right entry is accessed without runtime intervention. The page table organization used for translation in Hot Pages is similar to those used in virtual memory systems in contemporary microprocessors. A survey of six commercial memory management designs can be found in [8]. There is a large body of research related to hardware solutions for caching. Our work has been mostly influenced by research where compile time and runtime software mechanisms were used to improve the performance. The Shasta system [12] supports fine granularity sharing in software on cluster of ....
B. Jacob and T. Mudge. Virtual Memory in Contemporary Microprocessors. IEEE Micro, Aug. 1998.
Hardware/Software Architectures for Real-Time Caching - Jacob (1999) Self-citation (Jacob) (Correct)
No context found.
B. L. Jacob and T. N. Mudge. 1998b. "Virtual memory in contemporary microprocessors." IEEE Micro, 18(4):60--75.
Virtual Memory: Issues of Implementation - Jacob, Mudge (1998) (3 citations) Self-citation (Jacob Mudge) (Correct)
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B.L. Jacob and T.N. Mudge, "Virtual Memory in Contemporary Microprocessors," IEEE Micro, Aug. 1998, to appear.
Two-Level Address Storage and Address Prediction - Morancho, Llaberia, Olive (2000) (Correct)
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B. Jacob and T. Mudge. (1998). Virtual Memory in Contemporary Microprocessors. IEEE Micro, Vol 18(4), pp. 60-75.
Two-Level Address Storage and Address Prediction - Enric Morancho Jos (1999) (Correct)
No context found.
B. Jacob and T. Mudge. (1998). Virtual Memory in Contemporary Microprocessors. IEEE Micro, Vol 18(4), pp. 60-75.
Address Prediction and Recovery Mechanisms - Llena (2002) (Correct)
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B. Jacob and T. Mudge. (1998). Virtual Memory in Contemporary Microprocessors. IEEE Micro, Vol 18(4), pp. 60-75.
Transparent Operating System Support for Superpages - Navarro (2002) (4 citations) (Correct)
No context found.
B. Jacob and T. Mudge. Virtual memory in contemporary microprocessors. IEEE Micro, 18(4):60--75, July/Aug. 1998.
Scalable Vector Media-processors for Embedded Systems - Kozyrakis (2002) (7 citations) (Correct)
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B. Jacob and T. Mudge. Virtual Memory in Contemporary Microprocessors. IEEE Micro, 18(4):60--75, July 1998. 131
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