F. Kurdahi and C. Ramachandran, "LAST: A Layout Area and Shape Function Estimator for High Level Synthesis," in Proc. EDAC Conf., 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....given its structural implementation as a netlist of logic cells or blocks [JOLS92] Early approaches such as PLEST[KuPa89] analytically estimated the area of a component represented as a netlist of cells, and returned the area as a sum of the component s functional and estimated wiring areas. LAST[ChKu91] and TELE[ChKu92] use a combination of analytical and constructive techniques to predict the area and delay for a netlist of cells, while accounting for wiring. Recent work in layoutbased estimators[WCGa91] CWGa91] also provide area and delay values, given the structure of the modules ....

....through a design implementation (pin to pin, rising and falling) This calculation takes into account the fan out of the designs. Thus, DTAS provides a good source of sample design points for our approximations, using functional area and delay values. 6 To incorporate wiring effects, we use LAST[ChKu91] and TELE[ChKu92] which are estimators that provide more accurate metrics by considering not only functional blocks but also the wiring contributions. Since LAST and TELE have been benchmarked against actual layouts produced by commercial tools as well as against custom designed layouts, they ....

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F. J. Kurdahi and C. Ramachandran, "LAST: A Layout Area and Shape function esTimator for High Level Applications," Proc. of The European Conf. on Design Automation '91 pp351-355, February 1991.

....design by counting the number of functional units such as ALU, adders, multipliers, etc. and the number of clock cycles is no longer adequate. A more accurate layout evaluation is necessary. Recently, several tools capable of estimating area cost of a given RTL datapath have been developed[1] [2], 3] Most of these tools support standard cell design style and are not acceptable for the Macro Block designs. Besides, the main objective of algorithms implied in these tools is layout area minimization. As ASIC fabrication technology enters deep submicron (below 0:5 m) region, such an ....

F.Kurdahi and C.Ramachandran, "LAST: A Layout Area and Shape Function Estimator for High Level Applications", Proc. European Conf. on Design Automation, pp.351-355, 1991.

....given its structural implementation as a netlist of logic cells or blocks [13] Early approaches such as PLEST[15] analytically estimated the area of a component represented as a netlist of cells, and returned the area as a sum of the component s functional and estimated wiring areas. LAST[3] and TELE[4] use a combination of analytical and constructive techniques to predict the area and delay for a netlist of cells, while accounting for wiring. Recent work in layout based estimators[23] 5] also provide area and delay values, given the structure of the modules (components) these ....

....through a design implementation (pin to pin, rising and falling) This calculation takes into account the fan out of the designs. Thus, DTAS provides a good source of sample design points for our approximations, using functional area and delay values. To incorporate wiring effects, we use LAST[3] and TELE[4] which are estimators that provide more accurate metrics by considering not only functional blocks but also the wiring contributions. Since LAST and TELE have been benchmarked against actual layouts produced by commercial tools as well as against custom designed layouts, they provide ....

[Article contains additional citation context not shown here]

F. Kurdahi and C. Ramachandran, "LAST: A Layout Area and Shape function esTimator for High Level Applications," Proc. of The European Conf. on Design Automation'91 pp351-355, February 1991.

....approach for ratio cut partitioning. Second, a natural application of our work lies in the development of better predictive layout tools, which are critical to efficient search of the layout solution space. Most approaches are based on a mix of socalled constructive and analytic techniques [11], i.e. they meld a partial top down netlist partitioning structure with bottom up estimates for each of the leaves of the partitioning hierarchy, based on statistical models for particular place route strategies. Our work has deep consequences for both aspects of this estimation process: i) ....

....[3] which involve Rent based analysis. Wirelength estimates are intimately tied to layout wireability analysis [7] and moreover form the basis of analytic area estimation methods, e.g. El Gamal, Kurdahi, and Sastry [2] 10] 16] which are typically used to complement constructive approaches [11]. a variety of benchmark circuits. The Rent parameter can thus be used to objectively select among partitioning heuristics for use in a hierarchical layout approach. Before presenting experimental results, we briefly review a taxonomy of those partitioning algorithms which are of interest in the ....

F. J. Kurdahi and C. Ramachandran. LAST: A layout area and shape function estimator for high level applications. In Proc. Second European Design Automation Conf., February 1991.

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F. Kurdahi and C. Ramachandran, "LAST: A Layout Area and Shape Function Estimator for High Level Synthesis," in Proc. EDAC Conf., 1991.

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