JEAN-LOUP BAER AND WEN-HANN WANG. "On the Inclusion Properties for Multi-Level Cache Hierarchies". The 15th Annual International Symposium on Computer Architecture Conference Proceedings, Honolulu, Hawaii, IEEE Computer Society Press, May 30--June 2, 1988, pages 73--80.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....are in the on chip cache will be available. Note that it is not possible for a line to be in the on chip cache but not the crosspoint cache. In other words, if a line is in the on chip cache, it must be in the crosspoint cache. This important restriction has been called the inclusion property [BW88]. A sufficient condition for inclusion with direct mapped caches is stated in [WM87] A detailed study of inclusion for several cache organizations is presented in [BW88] Unfortunately, the authors of [BW88] appear to have misunderstood the results of [WM87] To determine if a particular ....

....is in the on chip cache, it must be in the crosspoint cache. This important restriction has been called the inclusion property [BW88] A sufficient condition for inclusion with direct mapped caches is stated in [WM87] A detailed study of inclusion for several cache organizations is presented in [BW88]. Unfortunately, the authors of [BW88] appear to have misunderstood the results of [WM87] To determine if a particular crosspoint cache line is in the on chip cache, the crosspoint cache uses the same address bits used to select the on chip cache entry to select an entry in this special memory. ....

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JEAN-LOUP BAER AND WEN-HANN WANG. "On the Inclusion Properties for Multi-Level Cache Hierarchies". The 15th Annual International Symposium on Computer Architecture Conference Proceedings, Honolulu, Hawaii, IEEE Computer Society Press, May 30--June 2, 1988, pages 73--80.

....be in the second level cache. Inclusion can be obtained by allocating space for everything that the first level cache allocates, and invalidating the corresponding first level cache entries on a secondlevel cache deallocation [Wil87] KH92] Gol92] or by having more complex secondlevel caches [BW88] WBL89] Special timing dependent inclusion is needed. The inclusion must be true when the write is being written to the cache, not when the write is put in a write buffer for later writing to the cache. Optimizations allowing reads to bypass writes in the write buffer, or a read fetch before ....

Jean-Loup Baer and Wen-Hang Wang. On the Inclusion Properties for Multi-Level Cache Hierarchies. In Conference Proceedings, The 15th International Symposium on Computer Architecture, pages 73--80, May 1988. BIBLIOGRAPHY 137

.... are not shown for these benchmarks) Although the contents of the first level cache and the second level cache can be mutually exclusive, inclusion between the sum of their contents and a third level of off chip caching can still be maintained for ease of constructing multiprocessor systems [1] by eliminating on chip cache lines which are not present off chip. 20 TRADEOFFS IN TWO LEVEL ON CHIP CACHING TPI (ns) Area (rbe) 10,000 100,000 1,000,000 5 10 15 . 1 Level Only Best 2 Level Config # 1:0 # 2:0 # 1:2 # 1:4 # 4:0 2:4 1:8 # 2:8 # 8:0 # 4:8 # 2:16 # 4:16 # 16:0 ....

Jean-Loup Baer and Wenn-Hann Wang. On the Inclusion Properties for Multi-Level Cache Hierarchies. In The 15th Annual Symposium on Computer Architecture, pages 73-80. IEEE Computer Society Press, June, 1988.

....read line transaction costs 246ns for a 100MHz processor. To that, the network latency must be added if one of the ends of the transaction, cache or memory, is at another node. The memory model is sequential consistency [12] The memory hierarchy satisfies the multilevel inclusion property [3]. So, the SCI coherency protocol actions affect only the secondary caches, thus called coherent caches. Coherency between primary and secondary caches is maintained by the cache controller. In order to simplify the simulator, it is assumed that on data accesses the concurrent instruction fetch ....

Jean-Loup Baer and Wen-Hann Wang. On the inclusion properties for multi-level cache hierarchies. In Proc. 15th Int. Symp. on Comp. Arch., pages 73--80, May 1988.

.... already been proposed (e.g. coalescing buffers or write caches [46] For the second class of unnecessary updates, other solutions have been pro 86 posed, such as competitive update protocols, where cache blocks are invalidated after receiving a number of updates without an intervening read [13]. Additionally, special care must be taken to ensure that update protocols support sequential consistency [61] discussed in the next section) With a GLOW update protocol, a sharing tree is constructed and subsequently used to distribute updates. There are two variations of the update protocol. ....

Jean-Loup Baer and Wen-Hann Wang, "On the Inclusion Properties for Multi-Level Cache Hierarchies." In Proceedings of the 15th Annual Symposium on Computer Architecture, May 1988.

.... the inclusion property is to probe the cache whenever there is a remote access request and broadcast invalidation signals to the cache when a line in the AM is replaced [Wil87] By attaching an inclusion bit, which indicates whether a copy of the data is in the cache or not, to each AM frame [BW88] excessive probing of the cache can be diminished while maintaining the inclusion property. However, additional intra node communication is still generated. Some studies [Joe95, SWCL95] on COMA consider relaxing the inclusion property somewhat to improve performance. To relax the inclusion ....

Jean-Loup Baer and Wen-Hann Wang. On the inclusion properties for multilevel cache hierarchies. In Proceedings of the 15th Annual International Symposium on Computer Architecture, pages 73--80. Computer Architecture News, 16(2), May 1988.

....that is, each cache at a given level contains a superset of the contents of the caches below it in the hierarchy. The primary reason for doing this is to limit unnecessary propagation of bus traffic from upper (i.e. towards the root of the tree) levels of the hierarchy to lower (cluster) levels [BW88] Because all caches obey inclusion, an upper level cache will not forward requests on its upper bus to its lower bus if the block in question is not present in its cache, because it is known not to be present in the caches below it. Note that inclusion is guaranteed not through associativity, ....

....an up todate copy of the data. A request must be sent to the cluster below, where the subblock might be present. Dirty Owned The subblock is valid, and the bus cache has an up to date copy. The subblock is not valid anywhere else in the system. A bus caches always maintains the inclusion property [BW88] with regard to the caches beneath it in the hierarchy. Table 6.1 shows the allowable cluster subblock states, given the bus subblock state. Lower level protocol The lower level protocol is very similar to that of the single bus subblock protocol as detailed in Chapter 3. Both the block and ....

Jean-Loup Baer and Wen-Han Wang. On the inclusion properties for multi-level cache hierarchies. In Proc. of 15th Int. Symp. on Computer Architecture, pages 73--80, 1988.

.... reduce the average memory access time by placing the working set of a program in a faster level in the memory hierarchy [KELS62, Wil65, Smi82a, SG83, Hil87, Hil88] A thorough research on cache organization and parameters has led to very low miss rates in current commercial microprocessors [BW88, PHH88, WBL89, BKB90, AP93, Sez93, BCcRJ 94, PK94, CG95, WSY95] See [EP88, Jou93] for a discussion on internal cache parameters, such as the interaction of write policy and line size. Software and hardware techniques such as [Goo83, CB92, CB94a, MLG92] have been devised to prefetch data from ....

Jean-Loup Baer and Wen-Hann Wang. On the inclusion properties for multilevel cache hierarchies. In Proceedings of the 15th Annual International Symposium on Computer Architecture, pages 73--80, Honolulu, Hawaii, May 30-- June 2, 1988. IEEE Computer Society TCCA and ACM SIGARCH. Computer Architecture News, 16(2), May 1988.

....Encore Multimax [Enco86] DEC Firefly [ThSt87] Xerox Dragon [McCr84] Berkeley SPUR, and SGI Power Series [Sili89] have been limited to at most 32 processors and often much less. 1.3.2. Hierarchical Protocols Hierarchical protocols make use of the cache hierarchy implied by a tree of buses [Wils87, BaWa88, VeJS89, ChGB91, YaTB92]. A cache hierarchy on a k ary n cube, implemented as either a grid of buses [GoWo88] or a set of rings [Scot91, Scot92] has a different tree per Ch. 1 7 memory module so that the tree root is not a network bottleneck. The network and the data s home location determine the tree s structure, but ....

....networks [Tane81] where the storage is divided into classes and the assignment of space is restricted, providing a partial order on the use of the classes. 1.3.2.1. Multilevel Inclusion One way to avoid the storage overhead of the naive solution is to maintain multilevel inclusion (MLI) [LaMu79, Wils87, BaWa88], where a cache stores a superset of all the lines stored in Ch. 1 8 descendant caches. When a cache line is purged, the purge is propagated to only those children that have copies. To save space, a parent need only store a vector if children have copies. To avoid storing data for every ....

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Jean-Loup Baer and Wen-Hann Wang, "On the Inclusion Properties for Multilevel Cache Hierarchies," Proceedings of the Fifteenth Annual International Symposium on Computer Architecture 16, 2 (May 1988), 73-80.

....parameter. Sizes investigated are 64, 128, 256 and, 512Kbytes. Main memory is simulated as if implemented with DRAMs with 8 way interleaving. On all three levels of the memory hierarchy, cache and memory lines (blocks) are 64 bytes. The memory hierarchy satisfies the multilevel inclusion property [1] and the SCI coherency protocol actions affect only the secondary caches, thus called coherent caches. The internal buses are 64 bits wide, except the processor primary caches which are 32 bits wide. The access latency for the secondary caches is 3 processor cycles. Loading a line from the ....

Jean-Loup Baer and Wen-Hann Wang. On the inclusion properties for multi-level cache hierarchies. In Proc. 15th Int. Symp. on Computer Architecture, pages 73--80, May 1988.

....bus, and also caches data for the processors in the cluster below it. To reduce bus traffic, all caches in the system are write back caches. Bus caches satisfy the inclusion property, that is, each cache at a given level contains a superset of the contents of the caches below it in the hierarchy [BW88] Inclusion is guaranteed through the actions of the protocol, as in [Wil87] When a bus cache replaces a block, it sends a message down that forces all processor caches below it to invalidate the block. Each bus cache has a dual directory so that operations on both busses it is connected to can ....

Jean-Loup Baer and Wen-Hann Wang. On the inclusion properties for multilevel cache hierarchies. In Proc. of 15th Int. Symp. on Computer Architecture, pages 73--80, 1988.

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Jean-Loup Baer and Wen-Hann Wang. On the Inclusion Properties for Multi-Level Cache Hierarchies. In Proc. of the 15th Annual International Symposium on Computer Architecture, pages 73-- 80, Honolulu Hawaii, June 1988.

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