F. Pong, M. Browne, G. Aybay, A. Nowatzyk, and M. Dubois. Design verification of the S3.mp cachecoherent shared-memory system. IEEETC, 47(1):135-- 140, 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....property to be correct because it was indirectly verified. For example, using emulation to construct a prototype of a multiprocessor and then executing benchmark programs to implicitly verify data coherence. References to prior work Correctness Property [14, 15] 16, 17] 18, 19] 20, 21] [22, 23] Data coherence I E E E Preservation of program order E E High level Properties Write serialization E E Wr i t e propaga t on I I I I Write atomicity E Absence of livelock deadlock I I I E E Implementation Specific Fairness Properties Single writer E E Unexpected message reception E E ....

....between the Verilog model and the abstracted SMV model. A three node system was modeled using two processors and an I O unit (for DMA requests) generating coherence traffic. In addition, the programmer input output (PIO) protocol was verified for two processors and two I O units. Pong, et al. [22] verified the S3.mp (Sun Scalable Shared memory MultiProcessor) directory based coherence protocol and Total Store Ordering (TSO) memory model using a combination of formal verification and conventional logic simulation. The approach used was similar to that was used for the SGI Challenge [30] ....

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F. Pong, M. Browne, G. Aybay, A. Nowatzyk, and M. Dubois. Design verification of the S3.mp cachecoherent shared-memory system. IEEETC, 47(1):135-- 140, 1998.

....system is correct for a given program execution, it must be correct for all executions and all programs. More recently, formal verification methods have been used to validate the coherence protocol of the SGI Origin2000 [15, 16, 17] and the Sun S3.mp (Sun Scalable Shared Memory Multiprocessor) [18, 19]. Eir iksson used the Symbolic Model Verifier (SMV) 20] to verify an abstract model of a three node Origin2000 system (two processors and an I O unit) Pong, et al. used the Mur [21] formal verification system to verify an abstracted three node S3.mp system. Each of these efforts needed to ....

....stimulus from the witness string shown in Figure 8. Quiescent E1(X:ShClean) Read(Y) on vc0 from P1 [13] E1 sending PInvalidate(X) to P1 [14] E1 sending MDrop(X) to M1 [15] E1 sending MRead(Y) to M2 [16] E1(Y:PendingReq) ReadExclResp(Y) on vc1 from M2 [17] E1 sending PReadResp(Y) to P1 [18] Quiescent to the cache coherence engine in the E chip. Soon, we will be using this approach to verify the cache coherence engine at the memory directory (the M chip) 6 Conclusion It is commonplace in computer architecture to use trace driven simulation to evaluate the performance of an ....

F. Pong, M. Browne, G. Aybay, A. Nowatzyk, and M. Dubois. Design verification of the S3.mp cache-coherent sharedmemory system. IEEETC, 47(1):135--140, 1998.

....the system is correct for a given program execution, it must be correct for all executions and all programs. More recently, formal verification methods have been used to validate the coherence protocol of the SGI Origin2000 [15, 16, 17] and the Sun S3.mp (Sun Scalable Shared Memory Multiprocessor) [18, 19]. Eir iksson used the Symbolic Model Verifier (SMV) 20] to verify an abstract model of a three node Origin2000 system (two processors and an I O unit) Pong, et al. used the Mur [21] formal verification system to verify an abstracted three node S3.mp system. Each of these efforts needed to ....

....stimulus from the witness string shown in Figure 8. Quiescent E1(X:ShClean) Read(Y) on vc0 from P1 [13] E1 sending PInvalidate(X) to P1 [14] E1 sending MDrop(X) to M1 [15] E1 sending MRead(Y) to M2 [16] E1(Y:PendingReq) RExclResp(Y) on vc1 from M2 [17] E1 sending PReadResp(Y) to P1 [18] Quiescent The witness strings from the Mur formal verification are post processed into stimulus encoded as Raven apply( and verify( calls. As an example, Figure 8 shows a snippet from a witness string as generated by the Mur formal verification tool. This string is converted into ....

F. Pong, M. Browne, G. Aybay, A. Nowatzyk, and M. Dubois. Design verification of the S3.mp cache-coherent sharedmemory system. IEEETC, 47(1):135--140, 1998.

....of new hardware. Furthermore, ARCHTEST is unable to detect deadlock, live lock, and loss of data coherence. More recently, formal verification methods have been used to validate the coherence protocol of the SGI Origin2000 [28, 29, 30] and the Sun S3.mp (Sun Scalable Shared Memory Multiprocessor) [31, 32]. Eir iksson used the Symbolic Model Verifier (SMV) 33] 10 to verify an abstract model of a three node Origin2000 system (two processors and an I O unit) Pong, et al. used the Mur [13] formal verification system to verify an abstracted three node S3.mp system. Each of these efforts needed to ....

F. Pong, M. Browne, G. Aybay, A. Nowatzyk, and M. Dubois. Design verification of the S3.mp cache-coherent sharedmemory system. IEEETC, 47(1):135--140, 1998.

....systems because of the state space explosion for large, complicated systems. For example, the SGI Origin 2000 coherence protocol is verified for a 4cluster system with one cache block [7] the memory subsystem of the Sun S3.mp cache coherent multiprocessor system is verified for one cache block [19], and the SPARC Relaxed Memory Order (RMO) memory consistency model is verified for small test programs [16] Park and Dill [17] propose using transaction aggregation to scale beyond finite state methods. Our approach can precisely verify the operation of a protocol in a system consisting of any ....

Fong Pong, Michael Browne, Andreas Nowatzyk, and Michel Dubois. Design Verification of the S3.mp CacheCoherent Shared-Memory System. IEEE Transactions on Computers, 47(1):135--140, January 1998.

....because of the state space explosion for large, complicated systems. For example, the SGI Origin 2000 coherence protocol is verified for a 4 cluster system with one cache block in [6] the memory subsystem of the Sun S3.mp cache coherent multiprocessor system is verified for one cache block in [17], the correctness of the Stanford FLASH coherence protocol is verified for small test programs and small configurations in [16] and the SPARC Relaxed Memory Order (RMO) memory consistency model is verified for small test programs in [15] In contrast, our approach can precisely verify the ....

Fong Pong, Michael Browne, Andreas Nowatzyk, and Michel Dubois. Design Verification of the S3.mp Cache-Coherent SharedMemory System. IEEE Transactions on Computers, 47(1):135-- 140, January 1998.

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F. Pong, M. Browne, G. Aybay, A. Nowatzyk, and M. Dubois. Design verification of the S3.mp cachecoherent shared-memory system. IEEETC, 47(1):135-- 140, 1998.

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F. Pong, M. Browne, A. Nowatzyk, M. Dubois, Design Verification of the S3.mp Cache Coherent Shared-Memory System. IEEE Transactions on Computers, Vol. 47, no. 1, Jan. 1998.

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