C. F. Joerg, "Design and implementation of a packet switched routing chip," Master's thesis, Massachusetts Institute of Technology, 1990. MIT/LCS/TR-482. 29  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Third, CR eliminates the need for acknowledgements by exploiting the underlying hardware handshakes for flow control. In previous schemes, each message requires a positive acknowledgement for buffer man agement or fault tolerance. Other mechanisms which provide hardware acknowledgements [36, 35] have been proposed, but they all consume substantial network bandwidth. 9 Summary We have presented Compressionless Routing, a combined framework for efficient deadlock free routing and fault tolerant communication. In contrast to other adaptive routing algorithms which prevent deadlock with ....

C. F. Joerg, "Design and implementation of a packet switched routing chip," Master's thesis, Massachusetts Institute of Technology, 1990. MIT/LCS/TR-482. 29

....to support any of a wide variety of other staged network topologies. Arctic uses a sophisticated buffer management scheme that greatly increases the effectiveness of its buffers and the utilization of network links. This scheme is similar to that developed by Joerg for the PaRC routing chip [4, 5] of the Monsoon multiprocessor. Arctic has a test and control system that is significantly more sophisticated than those in most previous chips. This system is accessible through a JTAG port. It is used to configure the chip, detect errors, count packet flow statistics, and handle certain errors. ....

....of the buffers contains a packet and since it assumes that the buffered packets are randomly addressed, but it does to the first order identify the advantage of Arctic s buffering system over a simpler FIFO system. A longer discussion of a similar analysis of this buffering system can be found in [4]. Related buffering schemes that avoid the problems of a simple FIFO system have been studied by other researchers [2, 10] The capabilities of these schemes differ from those of the PaRC Arctic scheme. For example, virtual channel schemes can be used to avoid routing deadlocks in mesh networks ....

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C. F. Joerg. Design and Implementation of a Packet Switched Routing Chip. TR 482, Laboratory for Computer Science, MIT, Cambridge, Mass., 1990.

.... replys, since replys by definition do not require further sends and can be handled right away 4 One way of giving preference to replys is by implementing two priority levels in the network [LAD 95] Another way is by preallocating the return path for a reply at the time the request is sent [Joe90] Finally, we can avoid the possibility of overflowing the memory, at some performance penalty, by limiting the number of messages outstanding between any two processors [ Any of these approaches could be incorporated into a network without significantly impacting our network interface ....

Christopher F. Joerg. The design and implementation of a packet switched routing chip. Technical Report TR-482, MIT Laboratory for Computer Science, Cambridge, MA, December 1990.

....there is no flow control at the switch level. By using a timeout, CR reduces unnecessary message drops. Third, CR eliminates the need for acknowledgements whereas in previous schemes, each message requires a positive acknowledgement. Though other mechanisms which provide hardware acknowledgements [10, 11] have been proposed, they all consume substantial network bandwidth. 8 Summary In this paper, we have presented Compressionless Routing, a combined framework for efficient deadlockfree routing and fault tolerant communication. In contrast to other adaptive routing algorithms which 5 Here, we ....

C. F. Joerg. Design and implementation of a packet switched routing chip. Master's thesis, Massachusetts Institute of Technology, 1990. MIT/LCS/TR-482.

....stability. Third, CR eliminates the need for acknowledgements by exploiting the underlying hardware handshakes for flow control. In previous schemes, each message requires a positive acknowledgement for buffer management or fault tolerance. Other mechanisms which provide hardware acknowledgements [36, 35] have been proposed, but they all consume substantial network bandwidth. 9 Summary We have presented Compressionless Routing, a combined framework for efficient deadlock free routing and fault tolerant communication. In contrast to other adaptive routing algorithms which prevent deadlock with ....

C. F. Joerg, "Design and implementation of a packet switched routing chip," Master's thesis, Massachusetts Institute of Technology, 1990. MIT/LCS/TR-482.

....testing support. The overall structure of Arctic is shown in Figure 5. Arctic uses a sophisticated buffer management scheme that greatly increases the effectiveness of its buffers and the utilization of network links. This scheme is similar to that developed by Joerg for the PaRC routing chip [5, 6] of the Monsoon multiprocessor. All buffering in Arctic is located in the input sections. Each input section contains three buffers; each capable of storing a maximum size packet. Each buffer is capable of storing either a priority packet or a normal packet. The last empty buffer is reserved for a ....

C. F. Joerg. Design and Implementation of a Packet Switched Routing Chip. TR 482, Laboratory for Computer Science, MIT, 1990.

....array called PaRC. It is a 4x4 packet routing switch that provides each port a high raw bandwidth (800Mbits sec) much of which is usable. For the links a high speed ECL gate array, called DLC, and flex cables were designed to reliably transfer data between boards. 2 The Packet Routing Chip PaRC [4] is a 4 by 4 packet switched routing chip. PaRC receives packets via one of its four input ports, stores the packet in an on chip buffer, and eventually transmits the packet via one of its four output ports. Each input port operates asynchronously and has enough buffering to store four packets. ....

C. F. Joerg. Design and Implementation of a Packet Switched Routing Chip. Technical Report LCS/TR-482, MIT, December 1990

....a region of the processor s virtual memory determined by the 16 high bits of an address. The processor sends commands to NIC via the 16 low bits of the address bus and the r w line. It sends data to NIC via the data bus. At the network end, NIC interfaces to a PaRC chip, a fast network switch [1]. The message format consists of five 32 bit words plus a 5 bit field typically used to indicate the type of message. The upper 8 bits of the first message word must contain the processor ID of the destination processor. The five words of a message can be loaded from 88100 s general registers. The ....

....By default, outgoing messages are not circuit switched 1 . The optional argument, cs flag, can cause a message to be circuit switched. The optional cs flag argument has only one possible value: cs The message is sent circuit switched. 1 For a description of PaRC s circuit switched mode, see [1]. Command Interactions: Concurrent NLOAD NSTORE, NNEXT, and NSEND commands can interact with each other. For example, if an NSTORE of an outgoing register is done at the same time as an NSEND, is the value sent in the message the old or the new value of the outgoing register. NIC will perform ....

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Christopher F. Joerg. "Design and Implementation of a Packet Switched Routing Chip." MIT/LCS/TR-482, December 1990.

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