J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance bdd package by exploiting memory hierarchy. In 33rd IEEE Design Automation Conference, 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....states. Examples of the memory saving approach are, e.g. in [6, 38, 14, 15, 27, 28, 10] In an auxiliary storage approach, one tries to exploit disk storage as well as distributed processors (network storage) to enlarge the available memory (and CPU) Examples of this approach are, e.g. in [25, 26, 21, 30, 22]. In this paper we explore the possibility of trading space with time in order to reduce the amount of memory needed to complete a given veri cation task. 2 More speci cally, our goal here is to devise a Breadth First State Space Exploration (BFS) algorithm with graceful degradation. In ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance bdd package by exploiting memory hierarchy. In 33rd IEEE Design Automation Conference, 1996.

....TOSCA Corresponding Author: Enrico Tronci. Tel: 39 0862 433129. Fax: 39 0862 433180. 2 In an auxiliary storage approach one tries to exploit disk storage as well as distributed processors (network storage) to enlarge the available memory (and CPU) Examples of this approach are, e.g. in [16, 17, 13, 21, 14]. In this paper we study the possibility of exploiting statistical properties of protocol transition graphs to improve state exploration algorithms. This is quite similar to what is usually done when optimizing a CPU on the basis of program pro ling [12] Our algorithm allows us to reduce the ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performance bdd package by exploiting memory hierarchy. In 33rd IEEE Design Automation Conference, 1996.

....of the popular symbolic model checker SMV, up to that SymQuest accepts formulas. The input language overlap has of course helped validating SymQuest. The core of a symbolic model checker is always made up of a BDD package. We did not develop our own package but relied on the Cal BDD package [17]. 4.2 Verifying # black can win and # white can win 4.2.1 Failure of Straightforward Symbolic Model Checking For our experiments, we mustered a PC with 1 GB of main memory. Two facts gave hope that we might be able to solve checkers: first, the possibility of using just 26 MB to represent the ....

J. Sanghavi, R. Ranjan, R.K. Brayton and A. Sangiovanni-Vincentelli. High performance BDD package by exploiting memory hierarchy. In Design Automation Conference (DAC96), pages 635--640, Las Vegas NV, June 1996.

....period of November 97 to June 98, at the University of British Columbia. The work is based on a project done by Jan Baekgaard Petersen, Yvonne Coady, and myself for the course CPSC513 at the University of British Columbia (UBC) in fall 97. Some of this work will appear as a tool paper in FMCAD98 [6]. The tool paper was coauthored by Alan J. Hu, my supervisor at UBC. 2 Introduction Propositional logic is a tool that can be used to solve various different problems. To make effective use of propositional logic, some kind of data structure is needed to represent and manipulate these formulae. ....

....Decision Diagrams. PhD thesis, Stanford University, January 1996. Published as Stanford University Tech Report STAN CS TR 95 1561. 5] C. Meinel and A. Slobodov a. Speeding up variable reordering of OBDDs. In International Conference on Computer Design, pages 338 343. IEEE, October 1997. [6] K. Milvang Jensen and A. J. Hu. BDDNOW: A parallel BDD package. In Formal Methods in Computer Aided Design, 1998. To Appear. 7] H. Ochi, K. Yasuoka, and S. Yajima. Breadth first manipulation of very large binary decision diagrams. In International Conference on Computer Aided Design, pages ....

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J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performanceBDD packageby exploiting memory hierarchy. In 33th DesignAutomation Conference, pages 635--640. ACM/IEEE, 1996.

....When not using reordering, the package is nearly as memory efficient as CUDD [7] the optimized sequential package on which it is based. With reordering, some additional memory overhead is incurred, similar to the technique Ranjan et al. 4] used to add reordering to the breadth first CAL package [6]. Another feature is the ability to perform several different BDD operations in parallel. Finally, the package is designed for portability: the API is a subset of the CUDD API, to simplify porting applications between our package and the popular CUDD package, and the parallel code uses the widely ....

.... d c d 1 d d d d 0 Fig. 1. A BDD and the resulting computation DAG for an operation on nodes a and d. Because we are targeting the package at networks of workstations, we expect communication to be expensive, so we want to exploit any locality of reference we can find. As explained in [6], the part of the unique table that will be accessed by an operation can be determined by the topmost variable of the BDDs involved. The cache can also be divided into parts storing only results for where the topmost variable falls in a certain range. Therefore, each machine stores the nodes for ....

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J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. Sangiovanni-Vincentelli. High performanceBDD packageby exploiting memory hierarchy. In 33th DesignAutomation Conference, pages 635--640. ACM/IEEE, 1996.

....find operations together with a regrouping garbage collector. These features lead to a factor of two improvement in speed on typical examples compared to existing libraries. 1 Introduction We describe a new BDD [3, 4] library that o#ers a several improvements compared to existing implementations [8, 11, 12]. Better locality We propose a novel scheme for reducing the number of nodes searched during each find operation. This is combined with a garbage collector that packs related nodes into nearby addresses. These improvements result in significantly greater locality of reference, which translates ....

....are automatically recognized as non garbage and are not swept by the garbage collector. We implemented a library based on these ideas and tested it by building BDDs for the standard combinational benchmark circuits. The new library is typically about twice as fast as existing implementations [8, 11, 12]. We assume that the reader is familiar with standard depth first BDD implementation techniques [2] 2 Data Cache Miss Patterns With today s high speed CPUs, the biggest performance bottleneck in BDD packages is the long latency of main memory. Thus, the main architectural decisions for the new ....

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Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, and Alberto SangiovanniVincentelli. High performance BDD package by exploiting memory hierarchy. In Proceedings of the 33rd Design Automation Conference, pages 635--640, June 1996.

....order are easy to make. Finally, on a more mundane but very practical level is research aimed at efficient implementation of BDDs. Brace et al. s paper [1] is the basis of most current implementations. Several papers have addressed making BDDs interact better with caches and virtual memory [21, 24, 18] and with parallel machines [27] Sentovich [26] gives a comparison of several popular BDD packages. B. Tricks for Combinational Equivalence The key idea behind most research to improve combinational equivalence checking is to take advantage of structural similarities between the circuits. The ....

J. V. Sanghavi, R. K. Ranjan, R. K. Brayton, and A. SangiovanniVincentelli, "High Performance BDD Package By Exploiting Memory Hierarchy, " DAC, 1996, pp. 635--640.

....The development of better implementation techniques for BDD packages also still continues. For example, new BDD 128 Formal Methods for the Verification of Digital Circuits packages are being developed which better exploit the memory and computing resources of a network of workstations [San96][Sto96] 7.2 Suggestions for future work Although the subject of this thesis is the development of formal verification methods, we frequently use simulation techniques in the presented methods. Simulation can be viewed as a general technique to sample the behavior of circuits. This serves two ....

J.V. Sanghavi, et al., "High Performance BDD Package by Exploiting Memory Hierarchy", Proc. 33rd ACM/IEEE Design Automation Conf., pp. 635--640, 1996.

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