D. Lanneer et al., "CHESS: Retargetable code generation for embedded DSP processors," in Code Generation for Embedded Processors. Norwell, MA: Kluwer, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....system attributes such as cost, performance, and power. However, such processor memory co exploration requires the capability to explicitly capture, exploit, and refine both the processor as well as the memory architecture. Recent approaches on language driven Design Space Exploration (DSE) 1] [3], 9] 14] 16] 23] 30] 34] 35] use Architectural Description Languages (ADL) to capture the processor architecture, generate automatically a software toolkit (including compiler, simulator, assembler) for that processor, and provide feedback to the designer on the quality of the ....

D. Lanneer et al. CHESS: Retargetable Code Generation for Embedded DSP Processors. Code Generation for Embedded Processors. Kluwer, 1997.

....With this work, we hope at least to conclude that there is a strong dependencyofdesign language to the design domain,and to demonstrate this with real applications. Domain specific languages have also been used at other abstraction levels. ASIP development environments such as LISA [12] and Chess [20] create both the processor architecture and a software development environment for it out of an instruction level processor description. In other cases, a domain specific language has also been used to describe the application at behavioral level (rather then architecture or instructionlevel) ....

Lanneer, D., J.Van Praet, A. Kifli, K.Schoofs,.W.Geurts, F.Thoen, and G.Goossens.CHESS: Retargetable Code Generation for Embedded DSP Processors. Code Generation for Embedded Processors. P. Marwedel, ed., KluwerAcademic Publishers,1995.

....in Verilog) On the other hand, the low level detail makes it much easier to synthesize hardware from the descriptions. B. nML The nML machine description language[9] is a high level machine description language that can be used to support automatically generated tools. It was used in the Chess[10] system for retargetable code generation as well as a variety of other tools[11] nML is very similar to Isdl except in the way constraints are handled. nML can only describe valid instructions. Therefore, it must work around invalid combinations by using additional rules, resulting in longer and ....

D. Lanneer et al., "CHESS: Retargetable Code Generation for Embedded DSP Processors," in Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995.

....for each instruction of the target processor simulating the impact of the instruction s execution on the processor s state. But, in case of pipelined architectures, this leads to enormous costs, because the C functions have to be copied for each pipeline stage. Another tool using nML is CHESS [17, 25], a retargetable code generation environment for xed point DSP processors developed at IMEC in Leuven, Belgium. CHESS is a mixed behavioral structural processor model supporting load store architectures and both homogeneous and heterogeneous register structures. The application is given as a C ....

....ow graph. The processor description is represented by a so called instruction set graph containing the register set and a compact description of the instruction set. CHESS supports automatic bit alignment and generates machine code to be simulated by the instruction set simulator CHECKERS [25]. FLEXWARE (SGS Thompson, Bell Northern Research) 29] uses a mixed model for behavioral structural processor description. Target processors are described by three separate structures: the set of available instruction patterns, a graph model representing the data path, and a resource classi ....

D. Lanneer, J. Van Praet, A. Ki i, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. Chess: Retargetable code generation for embedded dsp processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 85-102. Kluwer Academic Press, 1995.

....in the CBC SIGH SIM framework [5] and the CHESS system [8] CBC SIGH SIM consists of the retargetable code generator CBC and the instruction set simulator SIGH SIM. CHESS is retargetable code generation environment for fixed point DSP processors which is supported by the simulator tool CHECKERS [13]. The machine description language LISA [15] is the basis for a retargetable compiled simulator approach developed at RWTH Aachen, Germany. The project focuses on fast simulator generation for already existing architectures to be modeled in LISA. So far, LISA does not regard optimization ....

D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. Chess: Retargetable code generation for embedded dsp processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 85--102. Kluwer Academic Publishers, 1995.

....Accurate Performance Evaluation in Architecture Exploration 21 much easier to synthesize hardware from the descriptions. 6.2 nML The nML machine description language[7] is a high level machine description language that can be used to support automatically generated tools. It was used in the CHESS[8] system for retargetable code generation as well as a variety of other tools[9] nML is very similar to ISDL except in the way constraints are handled. nML can only describe valid instructions. Therefore, it must work around invalid combinations by using additional rules, resulting in longer and ....

D. Lanneer et al. CHESS: Retargetable Code Generation for Embedded DSP Processors. In Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995.

....optimizer is generated that is based on integer linear programming (ILP) It reads previously generated assembly programs and optimizes them. Experimental results show that large improvements can be achieved. In the past, research on retargetability has mainly focused on closed compilation systems [25, 26, 15, 14]. Using such a system in industry however mostly requires replacing the existing compiler infrastructure which causes high costs. Thus the use of retargetable compilers in industry is rare. Due to the postpass orientation, PROPAN can be integrated in existing tool chains with moderate effort and ....

....Work During the last years the development of retargetable code generation systems has gained increasing attention. In most approaches the code generation subtasks and interactions between them are addressed by graph based heuristic methods. The retargetable code generators MARION [4] CHESS [25], and CBC [8, 9] take phase interactions into account by heuristically estimating the effect of code generation decisions in one phase to other phases. The Express [14] and AVIV [15] compilers offer a heuristic coupling of code generation phases. In all these systems the quality of the generated ....

D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable Code Generation For Embedded DSP Processors. In [27], pages 85-- 102. Kluwer, 1995.

....experience. When compared to a traditional compiler approach, the ruledriven approach allows for faster development, and is easier to retarget. The quality of the results depend on the compiler development and optimization effort. When compared to model based retargetable compilation approaches [12][10] the rule driven approach requires retargeting development time; whereas, in principle, a model based compiler requires only a small change to the model to arrive at a new compiler. Also, the rich data structures used in those systems potentially allow for more sophisticated optimizations. ....

D. Lanneer, et. al., "Chess: Retargetable code generation for embedded DSP processors", in [8].

....our assembler generator tool and related issues. Conclusions and ongoing work on ISDL are presented in Section VI. II. RELATED WORK ON MDLS FOR EMBEDDED PROCESSORS We briefly review three representative research projects in the area of code generation for embedded systems: MIMOLA [2] CHESS [3], and FLEXWARE [4] The proceedings of the Dagstuhl Workshop [5] contain a collection of papers documenting several other contributors efforts. The MIMOLA design system is an environment for hardware software co design and includes a retargetable microcode compiler. The MIMOLA microcode ....

D. Lanneer et al. CHESS: Retargetable Code Generation for Embedded DSP Processors. In Code Generation for Embedded Processors, pages 85--102. Kluwer Academic Publishers, 1995.

....of the retargetable code generator CBC which uses a standard code generator generator for instruction selection, and the instruction set simulator SIGH SIM. Target architectures are described via nML, application programs are given in a high level language. Another approach using nML is CHESS [8, 12], developed at IMEC in Leuven, Belgium, a retargetable code generation environment for xed point DSP processors. CHESS uses a mixed behavioral structural processor model supporting load store architectures and both homogeneous and heterogeneous register structures. The application is given as a ....

....ow graph. The processor description is represented by a so called instruction set graph containing the register set and a compact description of the instruction set. CHESS supports automatic bit alignment and generates machine code to be simulated by the instruction set simulator CHECKERS [12]. One major shortcoming of nML is the disability to support pipelined instructions including ushes. LISA [18] a machine description language that does not suffer from this shortcoming. One other major advantage of this approach is the retargetable compiled simulator approach [17] Simulation ....

D. Lanneer, J. Van Praet, A. Ki i, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. Chess: Retargetable code generation for embedded dsp processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 85-102. Kluwer Academic Publishers, 1995.

....between multiple operations that execute the same function on different hardware resources. In addition, the data manipulation operations and data transfer operations are covered simultaneously. This optimizes the schedule from the start to include all required operations. 2.2. 3 Chess Chess [31] is a retargetable code generation environment for fixed point DSPs and ASIPs. It generates machine code for the target processor, described in the nML 55 language [14, 17] and provides feedback as to how well suited the target processor is for the given application. The nML target processor ....

D. Lanneer, J. Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable code generation for embedded DSP processors. In Code Generation for Embedded Processors, pages 85--102. Kluwer Academic Publishers, 1995.

....(IS) or the structure of the processor. nML [4] and ISDL [8] are examples of IS ADLs. In nML, the processor s IS is described as an attributed grammar with the derivations reflecting the set of legal instructions. nML has been used by the retargetable code generation environment CHESS [13] to describe DSP and ASIP processors. However, nML does not directly support multi cycle or multi word instructions. 3 ISDL also describes the processor in terms of its IS, with the goal of deriving a code generator ( 9] assembler and simulator. In ISDL, constraints on parallelism are ....

D. Lanneer, J. Van Praet, A. Kifli, K.Schoofs, W.Geurts, F. Thoen, and G. Goosens. CHESS: Retargetable Code Generation for Embedded DSP Processors. In P. Marwedel and G. Goosens, editors, Code Generation for Embedded Processors, chapter 5, pages 85-102. Kluwer Academic Publishers, Boston, Massachusetts, 1997.

....instruction level simulation, and compilation. 3.2. Compiler Oriented ADLs nML was proposed at TU Berlin [11] and used in the SIGH SIM instruction set simulator [12] and the CBC code generator [13] nML is also used in some other institutes. At IMEC, nML is also used in the CHESS code generator [14] and the CHECKERS instruction set simulator. At Cadence Design Systems, nML is used to generate an instruction set simulator, an assembler, and a disassembler [15] The main target processors of nML are DSPs and ASIPs. In nML, the behavior (i.e. the instruction set) of a processor is described in ....

D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable Code Generation for Embedded DSP Processors, In Code Generation for Embedded Processors (P. Marwedel and G. Goossens, ed.), Kluwer Academic Publishers, 1995.

....for each instruction of the target processor simulating the impact of the instruction s execution on the processor s state. But, in case of pipelined architectures, this leads to enormous costs, because the C functions have to be copied for each pipeline stage. Another tool using nML is CHESS [17, 25], a retargetable code generation environment for xed point DSP processors developed at IMEC in Leuven, Belgium. CHESS is a mixed behavioral structural processor model supporting load store architectures and both homogeneous and heterogeneous register structures. The application is given as a C ....

....ow graph. The processor description is represented by a so called instruction set graph containing the register set and a compact description of the instruction set. CHESS supports automatic bit alignment and generates machine code to be simulated by the instruction set simulator CHECKERS [25]. FLEXWARE (SGS Thompson, Bell Northern Research) 29] uses a mixed model for behavioral structural processor description. Target processors are described by three seperate structures: the set of available instruction patterns, a graph model representing the data path, and a resource classi ....

D. Lanneer, J. Van Praet, A. Ki i, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. Chess: Retargetable code generation for embedded dsp processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 85-102. Kluwer Academic Press, 1995.

....scheme introduced above can be used for different purposes. First of all, it can be used to characterize a given (retargetable) compiler, and indicate its scope of retargetability. As an example, Table 1 indicates the scope of retargetability of the current version of the Chess compiler [22]. Second, the classification scheme can be used to characterize a given processor and quickly identify the issues related to compiler development. In this case, the model gives an indication of how easily a compiler can be built for the processor, and which existing compilers might be suited. For ....

....grammar. The grammar s production rules define the composition of the instruction set, in a compact hierarchical way. The semantics of the instructions (e.g. their register transfer behavior and their assembly and binary encoding) are captured by attributes. nML is used by the CBC [36] and Chess [22] compilers. B. Processor Models for Compilation 1) Template Pattern Bases: A first approach, used by traditional compilers for general purpose CISC and RISC processors [28] 37] is to represent the target processor by means of a template pattern base, that essentially enumerates the different ....

[Article contains additional citation context not shown here]

D. Lanneer et al., "Chess: Retargetable code generation for embedded DSP processors," in Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds. Boston: Kluwer, 1995.

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D. Lanneer et al., "CHESS: Retargetable code generation for embedded DSP processors," in Code Generation for Embedded Processors. Norwell, MA: Kluwer, 1995.

No context found.

D. Lanneer et al., "CHESS: Retargetable code generation for embedded DSP processors," in Code Generation for Embedded Processors. Norwell, MA: Kluwer, 1995.

No context found.

D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, G. Goossens, CHESS: Retargetable code generation for embedded DSP processors, in: P. Marwedel, G. Goossens (Eds.), Code Generation for Embedded Processors, Vol. 317 of SECS, Kluwer Academic Publishers, 1995, pp. 85--102.

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D. Lanneer, J. Van Praet, A. Ki, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. Chess: Retargetable Code Generation for embedded DSP processors. In P. Marwedel, G. Goossens Code Generation for Embedded Processors, pp. 85-102, Kluwer Academic Publishers, 1995. 21

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D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable code generation for embedded DSP processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, volume 317 of SECS, pages 85--102. Kluwer Academic Publishers, 1995.

No context found.

Lanneer D., Praet J. V., Kii A., Schoofs K., Geurts W., Thoen F. and Goossens G. CHESS: Retargetable Code Generation for Embedded DSP Processors. In Code Generation for Embedded Systems. Kluwer Academic Publishers, 1995.

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D. Lanneer, J. Van Praet, A. Ki i, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable Code Generation For Embedded DSP Processors. In [25], pages 85-102. Kluwer, 1995.

No context found.

D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Guerts, F. Thoen, and G. Goossens, "CHESS: Retargetable code generation for embedded DSP processors," in Code Generators for Embedded Processors, P. Marwedel and G. Goossens, Eds. Amsterdam: Kluwer, 1995.

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D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, G. Goossens. CHESS: Retargetable Code Generation for Embedded DSP Processors. chapter 5 in [5].

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D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: Retargetable Code Generation For Embedded DSP Processors. In [25], pages 85--102. Kluwer, 1995.

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