| Ian MacIntyre and Bruno R. Preiss, The Effect of Cache on the Performance of a Multi-Threaded Pipelined RISC Processor, Department of Electrical and Computer Engineering University of Waterloo, 1991. |
....for the program to continue. The program initializes and temporarily enables or disables all FUs that operate on the stream, and then tells the FIFO to start outputting data at a certain rate. B. The Scheduler The most efficient way to run several programs on one CPU is to use a multi threaded CPU[1], 2] that has a separate set of registers (Program Counter, Flags, Stack) for every program (thread) To select the thread that will be run in the next clock cycle, a scheduler is needed. The scheduler computes the priority value of each thread, and then issues one instruction from that thread. ....
Ian MacIntyre and Bruno R. Preiss, The Effect of Cache on the Performance of a Multi-Threaded Pipelined RISC Processor, Department of Electrical and Computer Engineering University of Waterloo, 1991.
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