J. Vanhoof et al., High-Level Synthesis for Real-Time Digital Signal Processing. Boston: Kluwer, 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....changes when the designer should write the control description compared to then he she should write the datapath description. There is already a language for these kind of datapath descriptions, it is called Silage, and has been used as description language for HLS in the Hyper [89] and Cathedral [90] systems. Since ProGram also has the feature of WordAligning both input and outputs, the language cannot be adopted as is, but must be adapted to suit the style of ProGram. However, since it is a pure functional description language, it has great similarities with the production rules used in ....

J. Vanhoof, K.V. Rompaey, I. Bolsens, G. Goossens, H. De Man, "High-Level Synthesis for Real-Time Digital Signal Processing", Kluwer Academic Publishers, Netherlands, 1993.

....that have a low complexity and yet produce good quality schedules. The Time Constrained Scheduling (TCS) problem minimizes the number of functional units required to schedule a particular Data Flow Graph (DFG) within a specified number of time steps. Over the past few years a number of techniques [1, 2] have been proposed to solve the TCS problem. Heuristic list scheduling algorithms have been widely used for their low complexity and good performance. The complexity of a dynamic list scheduling algorithm, such as the Force Directed Scheduling (FDS) is 2 , where is the time ....

....scheduling algorithms have been widely used for their low complexity and good performance. The complexity of a dynamic list scheduling algorithm, such as the Force Directed Scheduling (FDS) is 2 , where is the time constraint and is the number of operations. Static list scheduling [1, 2] algorithms are the least complex among the known class of scheduling techniques with a linear time complexity of . Typically, static list scheduling algorithms, in order to maintain low complexity, do not perform any look ahead like that of FDS. The drawback is that, static list ....

J. Vanhoof, G. Goosens et al. . "High-Level Synthesis for Real-Time Digital Signal Processing". Kluwer Academic Publishers, 1993.

....from the Electrical Engineering Dpt. of the Technical University of Madrid. This research is part of the on going work on for a High Level Memory Management toolbox, called ATOMIUM [1] but it can be used also in other contexts as a generic stand alone technique. In ATOMIUM and Cathedral 2 3 [2], the address generation problem is solved after memory location assignment. The reason is that many possible location assignment schemes are feasible and exploring these is an extremely difficult problem on its own. Still, the potential address generation complexity is incorporated as well as ....

....after memory location assignment. The reason is that many possible location assignment schemes are feasible and exploring these is an extremely difficult problem on its own. Still, the potential address generation complexity is incorporated as well as possible already in this first stage also [2]. Relatively little research has been going on in terms of hardware address generation. A simplified model with address translations involving offsets is used in Mesa [3] in order to steer the clustering of array signals in memories. For real time signal processing systems, the required ....

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J.Vanhoof, K.van Rompaey, I.Bolsens, G.Goossens, and H.De Man. HighLevel Synthesis for Real-Time Digital Signal Processing. Kluwer Academic Publishers, Boston, 1993.

....A standard processor component requires software synthesis, which determines software execution order to satisfy resource and performance Fig. 2. The SpecSyn system design environment. constraints. We can obtain a custom processor s design through high level (behavioral) synthesis [1] [2], which converts the behavioral description into a data path structure of registertransfer (RT) components from a library, such as arithmetic and logic units, registers, counters, register files and memories, along with a finite state machine (FSM) controller that sequences the flow of data ....

J. Vanhoof, K. VanRompaey, I. Bolsens, and H. DeMan, High-level Synthesis for Real-Time Digital Signal Processing. Boston, MA: KluwerAcademic, 1993.

....for high level design capture without the need for digital system design skills. 2. Together with the easy programming environment, the compiler has to be sophisticated enough to produce area efficient, high speed datapath circuits. The development of High Level Synthesis in ASICDSP community [9] cannot simply be applied to the datapath designs on FPGA. Since the routing resource and logic resource are physically fixed, it is often hard to control or even predict the outcome of the layout synthesis on FPGA. If the routing resource is saturated in a certain location, this may lead to ....

....tool for multi FPGA designs on C language using the bit serial datapath module library. The 0 O r x[0] 0] x[0] 1] x[0] 2] x[1] 0] x[1] 1] x[1] 2] x[2] 1] x[2] 0] x[2] 2] u[2] 2] u[2] 1] u[2] 0] u[1] 2] u[1] 1] u[1] 0] u[0] 2] u[0] 1] u[0] 0] y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] yy y[8] y[9] 22 21 20 12 11 10 02 01 00 D D D D D D I I I for(k = 0; k tapY; k ) for(l = 0; l tapX 1; l ) for(l = 0; l tapX; l ) for(k = 0; k tapY; k ) FPGA set(y[0] 0) FPGA mult c(u[k] l] x[k] l] coef[tapY k 1] tapX l 1] WORD) ....

J. Vanhoof, K. V. Rompaey, I. Bolsens, G. Goossens and H. De Man," "High-Level Synthesis for Real-Time Digital Signal Processing," Kluwer Academic Publishers, 1993.

....result is kept in a register or in memory. The second phase compacts the sequence of operations. However, the two phases are interdependent; thus, Hartmann proposes a new scheduler that integrates data routing into scheduling. Hartmann s scheduler is embedded in the framework of the Cathedral II [56] sys47 tem. The Cathedral system is used to transform all operations in the application into operations available on the target processor. This includes converting operations not available on the target processor into multiple operations whose combination is functionally equivalent to the original ....

J. Vanhoof, K. Van Rompaey, I. Bolsens, G. Goosens, and H. De Man. High-Level Synthesis for Real-Time Digital Signal Processing. Kluwer Academic Publishers, 1993.

....specification of performance such as the schedule lengths of schedule sets Array Memory Mapping c b a c d d d b a c b a Grouped Arrays Orignal Arrays Memory Components Tiled Memory Figure 1. Array memory mapping in the behavior. The DSP synthesis algorithms described in [15] deal with the mapping of data streams (rather than arrays) to memories, and utilize the regularity of DSP access patterns to improve memory utilization. Unfortunately, not all applications can be easily described using streams, nor do all applications have the regularity of access of DSP ....

J. Vanhoof, K. Van Rompaey, I. Bolsens, G. Goossens, and H. De Man, High-Level Synthesis for Real-Time Digital Signal Processing, Kluwer Academic Publishers, Norwell, MA, 1993.

....that contain loops (for and while) require complex scheduling algorithms. In this paper, we present an algorithm that schedules a description in the form of a control data flow graph (CDFG) having loops with arbitrary nesting. Various approaches to scheduling in high level synthesis exist [1, 2, 7]. Loop scheduling has been addressed in [4, 3] Ku and De Micheli have proposed hierarchical scheduling for real time constraints [5, 6] In the presence of nested loops, the behavior specification is typically modelled as hierarchical CDFG structure where the CDFG in each level contains two types ....

Jan Vanhoof et al., "High Level Synthesis for Real Time Digital Signal Processing", Kluwer, 1993.

....and allow functionality and design constraints to be clearly stated. ii) Synthesis algorithms that perform design optimizations have been well established. iii) HLS allows the designer to explore a large design space in a relatively small amount of time. Scheduling is an important step in HLS [4, 1, 5]. Scheduling can be described as the process of dividing the DFG into time steps that correspond to clock cycles at the RTL level. Therefore, scheduling directly controls the throughput rate of the RTL design produced. However, for large designs the task of finding optimal schedules is a ....

Jan Vanhoof et. al., "High-Level Synthesis for Real-Time Digital Signal Processing", Kluwer Academic Publishers, 1993.

....1 Introduction The traditional view of high level or behavioral synthesis (HLS) 1] involves transforming the behavioral specification of a design into a register transfer level (RTL) specification which usually consists of a data path and a controller. Scheduling, as stated by many of our peers [2, 3, 4], is an important step in HLS. Scheduling can be described as the process of divid This research was partially supported by DARPA and monitored by the FBI, under contract number J FBI 93 116. y Author for Correspondence, 513) 556 4784 (Voice) 513) 556 7326 (FAX) Ranga.Vemuri UC.EDU ing ....

....time. Therefore, there exists a tradeoff between the scheduling time and design performance. A designer would try to exploit this tradeoff using good scheduling algorithms that need to be computationally simple, at the same time produce high quality schedules. A wide variety of algorithms [2, 3, 4] exist in the current literature to perform scheduling. In this paper we are primarily concerned about the List Scheduling (LS) algorithm [4, 2] that takes resource constraints (design area and component library) and tries to optimize the latency (or throughput) of the design. In short, a basic ....

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Jan Vanhoof et. al., "High-Level Synthesis for Real-Time Digital Signal Processing", Kluwer Academic Publishers, 1993.

....and an efficient algorithm has to be designed and verified. High level programming languages such as C, C and Pascal or a hardware description languages such as Verilog and VHDL can be used for this purpose. For signal processing applications, specialized programming languages such as SILAGE [91] have been developed to capture the signal processing algorithm in terms of difference equations which are used to describe time discrete systems. 2. Hardware structure description (RTL description) The algorithm description is converted into a hardware description to derive a basic hardware ....

.... High Level Synthesis Approach on FPGA Design Methods which automatically transform the algorithm level description (or a hardware behavioral description) into a hardware structural RTL description (register transfer level description) have been developed mainly for signal processing applications [91], 15] 50] For FPGA datapath synthesis, several tools are developed which perform this behavioral synthesis [82] 90] 1] 59] 33] 65] These behavioral synthesis systems are based on the recent work on high level synthesis. The main focus point of this research is to derive a ....

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Jan Vanhoof, et al., "High-Level Synthesis for Real-Time Digital Signal Processing," Kluwer Academic Publishers, 1993.

....functional specification into a structural description. There are several differences, though: 1. Most HLS systems do not accept full blown applications written in commonly used imperative languages. Usually their usage is restricted to input from small applications written in a special language [33], containing only one or a limited number of functions. 2. The MOVE framework limits the design space by using a templated TTA. As indicated in section 2.1 this has several advantages. It also does not make sense to include design points within the design space for which we can not compile and ....

Jan Vanhoof et al. High-Level Synthesis for Real-Time Digital Signal Processing. Kluwer academic publishers, 1993.

.... : for (y=1; y = 11; y ) for (x=1; x = 9; x ) Read from block (y 1,x 1) from old newframe; Predict block (y,x) Pop block from buffer and store at position (y 1,x 1) Push block (y,x) in the buffer; The buffer mechanism can be implemented by calculating the block addresses modulo 13 [20]. This results in a snake like operation of the buffer, as illustrated in Fig. 9. The resulting data flow is depicted in Fig. 10 where the 13 macroblocks are shown in the pipeline of the snake. Implementing this dataflow, taking into account extra possibilities of memory hierarchy optimisations, ....

J. Vanhoof, K. van Rompaey, I. Bolsens, G. Goossens, and H. De Man, High-Level Synthesis for Real-Time Digital Signal Processing, Kluwer Academic Publishers, Boston, 1993.

....scheduling 6.1 Overview After reducing SPAN, our approach tries to reduce the register requirements by rearranging some instructions without changing their iteration indices. This step is called incremental scheduling . Code rearranging strategies have previously been proposed by other authors [34, 35]. Such strategies fine tune the schedule by moving instructions. We consider two different moves of instructions in the schedule: ffl Re schedule: moves an instruction from the current cycle to another cycle if sufficient resources are available. ffl Swap: swaps two instructions in the ....

J. Vanhoof, K. Van Rompaey, I. Bolsens, G. Goossens, and H. De Man. High-Level Synthesis for Real Time Digital Signal Processing. Kluwer Academic Publishers, 1993.

....consists of several independent functional units (FU) controlled by one instruction word (IW) and connected by a fairly complex bus system (Fig. 2) In a DSP architecture these FUs are the Program Control Unit (PCU) Address Generation Units (AGU) Datapath Units (DPU) I O Units (IOU) etc. [Vanh92]. In some floating point DSPs, VLIW architectures are already applied [Madi95] These DSPs are usually used for highperformance applications, which require a high degree of flexibility. On the other hand, in high volume and low power products, e.g. in mobile communications, fixed point DSPs are ....

J. Vanhoof et al., High-level synthesis for real-time digital signal processing: the Cathedral-II silicon compiler, Kluwer Academic Publishers, 1992

....method is Enhanced Pipeline Scheduling [17] which relies on the motion of instructions around the loop. 1.3 ILP in high level synthesis Most HLS methods are oriented to data flow dominated designs. Although loop pipelining is commonly supported [13] 24] code motion is rarely addressed [54][70]. Nevertheless, some methods have been proposed to cope with behavioral descriptions containing conditional constructs, such as if then else . Path based Scheduling [12] and Tree based Scheduling [34] aim at optimizing the execution time of each path. Others, like conditional vector list ....

....in the remainder of this chapter, we focus on loop pipelining. A comprehensive study of loop unrolling can be found in [30] A common requirement when dealing with time constrained applications is that the total number of iterations of a loop should not depend on the setting of the data [36][70]. Therefore, we address the pipelining of loops whose total number of iterations can be determined at compile time (e.g. for loops) In the examples in this chapter, we assume a time constraint in the form of a specified upper bound for the DII of a loop. We also assume, for simplicity, that ....

J. Vanhoof et al., "High--Level Synthesis for Real--Time Digital Signal Processing", Kluwer Academic Publishers, pp. 12--26, 149--166, 1993.

....chip to chip communication. In the first part of our paper, we will briefly decribe our work on Field Programmable MultiChip Module (FPMCM) The last two problems have long been one of the central issue in researches concerning FPGA. The development of High Level Synthesis in ASIC DSP community [14] cannot simply be applied to the datapath designs on FPGA. Since the routing resource and logic resource are physically fixed, it is often hard to control or even predict the outcome of the layout synthesis on FPGA. If the routing resource is saturated in a certain location, this may lead to ....

J. Vanhoof, K. V. Rompaey, I. Bolsens, G. Goossens and H. De Man," "High-Level Synthesis for Real-Time Digital Signal Processing," Kluwer Academic Publishers, 1993.

....their assigned tasks as they maintain multiple execution flows. General purpose, programmable processors (soft ware processors) and communication units (buses, etc. execute serially their assigned functionalities. The semantics of our execution model is similar to that of a single rate system [7]. It assumes that each node is executed not more than once for each traversal of the graph. Scheduling with data and control dependencies Figure 2 presents the Gantt chart for a correct, possible schedule for the example in Figure 1. This figure does not include activations of nodes 1, 5, 8, and ....

J. Vanhoof, et al. High-Level Synthesis for Real-Time Digital Signal Processing. Kluwer Academic Publishers, 1993.

....optimisation tasks. The Cathedral 3 high level synthesis system, developed in our lab, is based on the above concepts. It is targeted to high speed real time signal processing functions, which have a low potential for time multiplexing [39, 57] and extends the older Cathedral 2 methodology [52] which is embedded in the commercial Mistral 2 environment of EDC Mentor [40] Cathedral 3 has been used intensively in the mobile terminal design. Eight different accelerators have been synthesised that deal with the high speed signal processing functions as defined in the previous sections. 6.2 ....

J. Vanhoof et al., "High-level synthesis for real-time digital signal processing " Kluwer Ac. Publ. Boston,1993.

....strategy to adapted the design methods to a specific application domain. Different approaches for partitioning and synthesis as well as for target architectures have been proposed, e.g. for control oriented designs [4, 1] data flow oriented designs [14, 3] and real time constrained designs [20, 27]. We applied this principle of specialization to prototyping, i.e. the prototyping architecture is specialized in respect of the target architecture. This idea brought us to the FLYSIG approach. The main advantages are: the elimination of all design tasks related to FPGA prototyping from the ....

J. Vanhoof, K.V. Rompaey, I. Bolsens, G. Goosens, and H. De Man. High-Level Synthesis for Real-Time Digital Signal Processing. Kluwer Academic Publishers, Boston/Dordrecht/ London, 1993.

....commercial available and from University, that deal with problems of High Level Synthesis. Among the commercial, Synthesia s SYNT [SYNT 96] and Synopsys Behavioural Compiler [SynBC 94] deals with the problems of High Level Synthesis. Available from University are the Hyper [Hyper 93] Cathedral [VRBGM 93] and CAMAD [Peng 87] systems. These systems have many things in common and they differ also in many ways. Section 1.1. covers the utilisation of a designers knowledge of a design domain. To add experienced designers knowledge on how to design circuits in a given domain to a tool, would be a ....

....Chippe [BrGa 90] uses rules to perform different optimisations in five different synthesis phases and to control the synthesis process which is based on iterative improvement. The BUD system [MFKo 91] encapsulates design information on layout level in order to improve the design. Cathedral [VRBGM 93] uses a rule base for type selection and a user defined set of rules in design scripts for setting synthesis constraints. Most papers on how to perform High Level Synthesis [BhLe 90] MFPC 90] PaKn 89] and to do design optimisation using transformations presented the resent years, for instance ....

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J. Vanhoof, K.V. Rompaey, I. Bolsens, G. Goossens & H. De Man, "High-Level Synthesis for Real-Time Digital Signal Processing", Kluwer Academic Publishers, Netherlands, 1993.

....This is unfeasible in video and image processing applications, and the like. Little work has been performed in the HLMM domain within a high level or system level synthesis context. Most effort up to now has concentrated on detailed in place storage of M D signals to reduce the memory size [27, 28, 14, 21] and on address cost reduction by optimising the address sequences and the address generation circuitry [11] However, on top of this it is possible to identify several other crucial synthesis tasks. In particular, we have addressed global control flow optimisations intended to reduce the total ....

....order imposed by the dependence relations existent in the code, there is much freedom left in the execution ordering. This can be exploited by a designer in order to meet his goals e.g. to take profit of the parallelism hidden in the code. The current allocation tool of the CATHEDRAL system [28] cannot handle the example of Fig. 1 if e.g. lines (1) and (5) are interchanged, as this tool interpretes the given code procedurally. It finds out that signal optDelta[0] is consumed before being produced and exits, as the only operation ordering taken into account is that one given initially. ....

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J.Vanhoof, K.Van Rompaey, I.Bolsens, G.Goossens, H.De Man, "High-level synthesis for realtime digital signal processing" Kluwer Academic Publishers, Boston, 1993.

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J. Vanhoof et al., High-Level Synthesis for Real-Time Digital Signal Processing. Boston: Kluwer, 1993.

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Jan Vanhoof et al. High-Level Synthesis for Real-Time Digital Signal Processing. Kluwer academic publishers, 1993.

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J. Vanhoof, K. V. Rompaey, I. Bolsens, G. Goossens, and H. De Man. High-level Synthesis for Real-time Digital Signal Processing. Kluwer Academic Publishers, 1993.

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