O. Temam, C. Fricker, and W. Jalby. "Cache interference phenomena". In SIGMETRICS '94: Proceedings of the 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....on a specific computer, determine the portions of the code or the data structures that result in a large fraction of the cache misses, and then optimize these code segments and or data structures. Trace driven simulations have also been used to develop analytical models of cache behavior. See [4, 15, 19, 22 24], for example, for some ways in which trace driven simulators have been used in cache performance enhancement studies. La Maxca and Ladner [13] develop a model for a single level direct mapped cache. They use this model to analyze the performance of binary heaps and cache aligned d heaps. LaMarca ....

O. Ternare, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the 1993 ACM SIGMETRICS: Conference on Measurement and Modelling of Computer Systems, pages 261-271, Nashville, Tennessee, 1994.

....simulators and pro lers. Porter eld [19] introduces the concept of over ow iteration for predicting the miss ratio for a fully setassociative LRU cache. Ferrante, Sarkar and Thrash [10] provide closed form formulas to estimate the capacity misses of a loop nest. Temam, Fricker and Jalby 10 [24] also consider con ict misses but for a subset of array references studied in this paper. Wolf and Lam [30] propose to use vectors to describe data reuse for uniformly generated references in a perfect loop nest. They also use reuse vectors to derive an estimate of cache misses to guide their data ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In ACM SIGMETRICS'94 Conference on Measurement and Modeling of Computer Systems, pages 261-271, May 1994.

....low power, and low implementation cost. Thus, for these caches, interference misses can dominate the cache behavior, particularly for array based codes. It should be stressed that since the cache interferences occur in a highly irregular manner, it is very difficult to capture them accurately [11]. Ghosh et al. proposed cache miss equations in [4] as an analytical framework to compute potential cache misses and direct code optimizations for cache behavior. 3.2 Data Reuse and Data Locality Data reuse and data locality concepts are discussed in [12] in detail. Basically, there are two ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proc. of ACM SIGMETRICS Conference on Measurement & Modeling Computer Systems, 1994.

....to increase in respect to processor clock speeds utilizing the cache to its full potential is more and more essential. Yet cache behavior is extremely difficult to analyze, reflecting its unstable nature in which small program modifications can lead to disproportionate changes in cache miss ratio [2, 12]. A method of evaluating cache performance is required, both to give quantitative predictions of miss ratio, and information to guide optimization of cache use. johndcs.warwick.ac.uk Traditionally cache performance evaluation has mostly used simulation, emulating the cache effect of every ....

.... which analytical models have been employed has been in studying the cache performance of particular types of algorithm, especially in the analysis of blocked algorithms [9, 3, 5] Attempts have been made at creating general purpose models that are both accurate and expressive, with some success [12, 6, 7], but in all cases limited to describing direct mapped caches. In this work we present novel analytical techniques for predicting the cache performance of a large class of loop nestings, for the general case of set associative caches (i.e. with direct mapped as the case with associativity one) ....

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Olivier Temam, Christine Fricker, and William Jalby. Cache interference phenomena. In Proceedings ofACM SIGMETrICS, pages 261-271, 1994.

....same cache line. Self interference denotes conflicts that are caused by accesses to the same array. Cross interference occurs when different arrays compete for a cache line. For details on cache architecture we refer to [8] a comprehensive analysis of cache interference phenomena can be found in [16]. By cache thrashing we denote the situation when on every iteration of the innermost loop, references cause data to be evicted from the cache. Array references are generated by an affine mapping of the loop counter vector [18] Linear references differing only in a constant displacement are ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the Sigmetrics Conference on Measurement and Modeling of Computer Systems, pages 261--271, New York, NY, USA, May 1994. ACM Press.

....of memory locations for the same cache line; they do not occur in fully associative caches. Self interference denotes conflicts that are caused by accesses to the same array. Cross interference occurs when different arrays compete for a cache line. A comprehensive analysis can be found in [TFJ94] By cache thrashing we denote the situation when on every iteration of the innermost loop, references cause data to be evicted from the cache. This notion corresponds to severe conflicts in [RT98] Temporal reuse of data in the cache occurs when the same data item is accessed several times. ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the Sigmetrics Conference on Measurement and Modeling of Computer Systems, pages 261--271, New York, NY, USA, May 1994. ACM Press.

....identifying conflicting data structures cannot be done relying just on hardware counters for any of the current microprocessors. Moreover, these tools can only analyze the locality exploited by the memory hierarchy of the actual microprocessor. Tools based on a static locality analysis (e.g. [18][7] This approach is very fast since it has a negligible slowdown. However, it may be inaccurate for some programs due to the lack of information at compile time. For instance, loop bounds, initial addresses of data structures, size of array dimensions, etc. may be unknown at compile time, which ....

O. Temam, C. Fricker and W. Jalby, "Cache Interference Phenomena", in ACM Sigmetrics Conf. on Measurement and Modeling of Computer Systems, May 1994

....microprocessor. In addition they provide a limited set of results depending on the particular counters provided by a particular machine. Information, like conflict misses between two particular memory references cannot be 8 obtained with current hardware counters. Some static analysis techniques [21] have limited accuracy. Due to unknown information at compile time. For instance, unknown loop bounds or unknown initial addresses of data structures can degrade the accuracy of the results. A solution to this problem is to use hybrid techniques such as SPLAT [19] SPLAT is a static analysis ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proc. of ACM SIGMETRICS Conf. on Measurement and Modeling of Computer Systems, May 1994.

....of cache simulators and pro lers. Porter eld [17] introduces the concept of over ow iteration for predicting the miss ratio for a fully set associative LRU cache. Ferrante, Sarkar and Thrash [8] provide closed form formulas to estimate the capacity misses of a loop nest. Temam, Fricker and Jalby [21] also consider con ict misses but for a subset of array references studied in this paper. Wolf and Lam [27] propose to use vectors to describe data reuse for uniformly generated references in a perfect loop nest. They also use reuse vectors to derive an estimate of cache misses to guide their data ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In ACM SIGMETRICS '94 Conference on Measurement and Modeling of Computer Systems, pages 261-271, May 1994.

....show that the simulation replicates the broad features of the measured data it is evident that the simulation is the more accurate when communications is much less important than the work being done. There are we believe two causes for this. The first is that the single processor memory hierachy[18, 9, 1] (cacheing) is becoming important and the second is that the detailed working of the interconnect network is beginning to show. The cache effect can be modelled by introducing structure to the memory access times, but this introduces parameters that are difficult to measure. The network ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the ACM SIGMETRICS conference on Measurement and Modelling of Computer Systems, 1994.

....and engineers. Because of trends in computer architectures, lessons learned here are also likely to prove very useful for other application domains, including image processing and high performance databases. 6 Related Work There has been much work on improving locality in scientific applications [3, 24, 25, 26, 39, 40, 57, 67, 69, 70, 79, 87]. Here we will focus on the work which is most relevant to our proposed research. A number of researchers have investigated tiling as a means of exploiting reuse. Lam, Rothberg, Wolf show conflict misses can severely degrade the performance of tiling [51] Wolf and Lam analyze temporal and ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the 1994 ACM SIGMETRICS Conference on Measurement & Modeling Computer Systems, Santa Clara, CA, May 1994.

....This model is too expensive to be used in practice but we include it since it is more accurate than any other static model. We interpret results obtained for the simulator as upperbound results with which we can compare other models. We are currently implementing a sophisticated cache model [16] that is reported to be almost as accurate as a real simulator. Second, as a realistic case, we use a simple model proposed by Coleman and McKinley [7] that is inexpensive but less accurate than a simulator. It uses an approximation of the working set WS and selects the tile size giving rise to ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proc. SIGMETRICS'94, pages 261--271, 1994.

....; TB ) where TX is the time that process X takes to complete, X:Y denotes the sequence of two processes, XjY denotes parallel execution of two processes. Forward computation of TX is possible (within reason) using analytical techniques and rigorous mathematics like that developed in [1] 18] and [15] [4] 14] The segregation of memory access makes this prediction significantly more simple (and computationally cheaper) especially for the inner loops that are often the most important. This model assumes that processes A and B can 148 D. May et al. Effective Caching for Multithreaded ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proc. ACM SIGMETRICS, on measurement and modelling of Comp. Sys., Nashville, May 1994. ACM.

.... [1, 17, 24, 25] Data transformations have also been combined with loop transformations [5, 16] Severalcachecapacity estimation techniques havebeen proposed to help guide data locality optimizations [9, 33] These techniques can also be enhanced to take into account limited cache associativity [8, 30]. More recently, Ghosh et al. developed symbolic cache representation which are highly accurate in predicting cache misses [11, 12, 13] Their cache miss equations can be used to predict the number of cache misses for a computation, and also be used to guide compiler transformations such as tiling ....

O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the 1994 ACM SIGMETRICS Conference on Measurement & Modeling Computer Systems, Santa Clara, CA, May 1994.

....these benchmarks than execute them. The cache simulator was used in this study to identify the limits to filtering based on a very accurate cache model versus a simpler and faster one. We are considering other modeling techniques, such as Cache Miss Equations [11] or similar techniques proposed in [20, 10] that yield very accurate cache miss rate with much lower cost. Using these techniques we believe that the cost of Post SIM1, Post SIM2 and Pre SIM will be as low as that of Post MOD and Pre MOD. We intend to quantify the amount of time saved relative to Execution Only Algorithm using these ....

O. Temam, C. Fricker, and W.Jalby. Cache interference phenomena. In Proc. SIGMETRICS'94, pages 261--271, 1994.

....coherence: Keywords: Multiprocessor memory sytem, performance evaluation, data layout. 1 Introduction The purpose of this work is to study the feasibility of cache performance analysis and prediction in the context of multiprocessors. This work has already been conducted for uniprocessors [1], but it is not straightforward that it can be extended to multiprocessors. Besides, there were many studies on the nature, importance of each type of cache misses for uniprocessors [2, 3] so that the difficulties in elaborating a cache model (i.e. cache interferences) could be easily ....

....loop nest be serialized (1) ffl The loop nest can be parallelized but suffers from true sharing (2) ffl The loop nest can be split in independent sets after being restructured (3) Loop nest without dependences. 4) Case (1) sums up to a monoprocessor problem, and the reader is referred to [1], where the performance evaluation of a monoprocessor cache memory is conducted. If a loop nest corresponds to case (2) it clearly constitutes a performance bottleneck. The purpose of this paper is to analyze less wellunderstood cases that fall into cases (3) and (4) For cases (3) and (4) the ....

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O. Temam, C. Fricker, and W. Jalby. Cache Interference Phenomena. In Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 1994.

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O. Temam, C. Fricker, and W. Jalby. "Cache interference phenomena". In SIGMETRICS '94: Proceedings of the 1994.

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O. Temam, C. Fricker, and W. Jalby. Cache Interference Phenomena. In In Proceedings of the 1994.

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O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the Sigmetrics Conference on Measurement and Modeling of Computer Systems, pages 261--271, New York, NY, USA, May 1994. ACM Press.

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O. Temam, C. Fricker, W. Jalby, Cache interference phenomena, in: Proc. Sigmetrics Conference on Measurement and Modeling of Computer Systems, ACM Press, 1994, pp. 261--271.

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Temam, O., Fricker, C., Jalby, W.: Cache Interference Phenomena. In: Proc. Sigmetrics Conference on Measurement and Modeling of Computer Systems, ACM Press (1994) 261--271

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O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the Sigmetrics Conference on Measurement and Modeling of Computer Systems, pages 261--271, New York, NY, USA, May 1994. ACM Press. 27

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O. Temam, C. Fricker and W. Jalby, "Cache Interference Phenomena," Proc. ACM SIGMETRICS, pp. 261271, May 1994.

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O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In Proceedings of the Sigmetrics Conference on Measurement and Modeling of Computer Systems, pages 261--271, New York, NY, USA, May 1994. ACM Press.

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O. Temam, C. Fricker, and W. Jalby. Cache interference phenomena. In ACM SIGMETRICS'94 Conference on Measurement and Modeling of Computer Systems, pages 261--271, 1994.

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