A. J. Smith, "Second bibliography for cache memories," Computer Architecture News, vol. 19, no. 4, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....5 discusses performance techniques motivated by the results and insights of Section 4. Finally, Section 6 summarizes and suggests further uses of DTrack. 2 Related Work A common method of producing aggregate memory statistics is through simulation, of which we cite a few representative samples [1, 7, 19, 3]. More sophisticated cache memory behavior analysis tools have been developed [20, 8, 11, 12, 13, 14] and this section compares DTrack to this prior work. Our work di ers from these tools in that we consider pointer data structures in addition to arrays, and show that aggregate statistics obscure ....

A. J. Smith. Second bibliography on cache memories. Computer Architecture News, 19(4):154-182, June 1991.

....is at most 1.024 times that of optimal for the Ultrix traces (as F varies) and at most 1.02 times that of optimal for the Sprite traces. 5 Related Work Caching has been studied extensively in the past and there is a large body of literature on caching ranging from theory [2, 8] to architecture [21] to file systems [11, 16, 4] etc. Prefetching has also been studied extensively in various domains, ranging from, uni processor and multi processor architectures [20, 5, 3, 22, 24] to file systems [19, 10, 23] to databases[6, 17] and beyond. Sequential one block lookahead was first proposed in ....

Alan J. Smith. Second bibliography on cache memories. Computer Architecture News, 19(4):154--182, June 1991.

....a good overview of caches. Because caches are such an important part of the memory hierarchy, caches have been studied heavily and many articles have been written on the subject. A list of many of the articles related to caching can be found in bibliography lists compiled by Alan Smith ( Smi86] Smi91] 1.1 Caches Caches work because the reference pattern of most programs have locality. Locality consists of two parts: temporal and spatial. Temporal locality occurs because a recently referenced object is likely to be referenced again in the near future. Therefore, a referenced object is ....

A. J. Smith. Second Bibliography on Cache Memories. Computer Architecture News, 19(4):154--182, June 1991. BIBLIOGRAPHY 142

....associated with distinct processors in a multiprocessor. The hardware cost for storing these tags may be quite high when the cache line size is in the range of 16 to 64 bytes. Surprisingly, for the ten last years, there has been very few studies on limiting the tag cost and volume for caches [14, 15]. In order to reduce this tag storage cost, sectors have been used in many cache designs for more than 20 years. A sector consists in several contiguous cache lines associated with a single address tag. Using sectored caches instead of a classical cache structure significantly decreases the tag ....

A.J Smith "Second bibliography on Cache Memories" Computer Architecture News, June 1991

....be high when the line size is in the range of 16 to 64 bytes. The tag implementation cost is a major issue in many cache designs and particularly for the design of L2 cache controllers; but surprisingly, for the ten last years, limiting the tag implementation cost for caches has not been studied [14, 15]. In order to reduce this tag implementation cost, sectors have been used in many cache designs for more than 20 years. A sector consists of several contiguous cache blocks associated with a single address tag 1 . The size of the tag array in a sectored cache is significantly lower than the size ....

A.J. Smith "Second bibliography on Cache Memories " Computer Architecture News, June 1991

....and pass the data written on to lower levels in the memory hierarchy (write invalidate vs. no write invalidate) Different combinations of these three variables can result in a 2:1 range in cache miss rates for some applications. Out of the hundreds of papers on caches in the last 15 years [15, 16], Smith [13] was the only paper to exclusively deal with write issues. This paper discussed write buffer performance for write through caches, but did not investigate merging of pending writes to the same cache line by a write buffer. Smith [14] and Goodman [7] both have a section on write back ....

Smith, Alan J. Second Bibliography on Cache Memories. Computer Architecture News 19(4):154-182, June, 1991.

....associated with distinct processors in a multiprocessor. The hardware cost for storing these tags may be quite high when the cache line size is in the range of 16 to 64 bytes. Surprisingly, for the ten last years, there has been very few studies on limiting the tag cost and volume for caches [14, 15]. In order to reduce this tag storage cost, sectors have been used in many cache designs for more than 20 years. A sector consists in several contiguous cache lines associated with a single address tag. Using sectored caches instead of a classical cache structure significantly decreases the tag ....

A.J Smith "Second bibliography on Cache Memories" Computer Architecture News, June 1991

....used to design profiles for any general client server system. Information gained from such profiles would be of great help in designing strategies for task partitioning and load balancing. 60 5. FACTORS IN MEMORY SYSTEM DESIGN Cache memory is frequently used to improve memory access performance [65, 66, 67, 68, 69, 70, 71, 72]. Graphical displays make use of a specialized frame buffer memory to maintain the bit map image of the display. However, the benefit of using conventional caches is not clear for frame buffer accesses since these accesses have large working sets and are mainly writes. As computers with graphical ....

A. Smith, "Second bibliography on cache memories," Computer Architecture News, vol. 19, pp. 154--182, June 1991.

....design. Memory hierarchies composed of cache memories are so crucial to high performance computer architecture design that performance evaluation of cache memories has received phenomenal attention. In 1991, Smith catalogued 487 technical papers and reports that dealt with some aspect of caching [28]. This chapter addresses the problem of deriving prototypes of memory systems designed with caching. To do this requires measurement of the performance of a large number of cache designs. This cache performance evaluation process must be fast yet accurate. The importance of accuracy is ....

A. J. Smith, "A second bibliography on cache memories," Comput. Architecture News, vol. 19, pp. 138--153, June 1991.

....better than a naive strategy, both theoretically and in practice. In the systems community, caching and prefetching have been known techniques to improve the performance of storage hierarchies for many years [50, 1, 17] The breadth of application of these techniques has ranged from architecture [46] to database systems [47, 11, 39, 13] to file systems [17, 33, 24, 37, 48, 6, 21, 9, 42] and beyond. A recent trend in this research is to use applications knowledge about their access patterns to perform more effective caching and prefetching [6, 9, 41, 42, 23, 34] Our practical motivation for ....

Alan J. Smith. Second Bibliography on Cache Memories. Computer Architecture News, 19(4):154--182, June 1991.

....Preprint 26 August size, degree of associativity, and block replacement strategy therefore must be carefully selected to ensure good cache behavior. These design parameters and their effects on cache hit rates and processor to memory traffic have been and continue to be the focus of many studies [1,2]. While the possibility exists to craft an optimal cache organization for a given program workload, cache misses are still inevitable and they occur for various reasons. One fundamental reason is the cold start or compulsory effect: the first time a cache block is requested, such data is likely to ....

A.J. Smith, Second Bibliography on Cache Memories, Computer Architecture News , Jan 1991.

....in the more practical online case. 5 Related work Caching and prefetching have been known techniques to improve storage hierarchies for many years [47, 2, 19] In architectures, the work on caching and prefetching has been focussed on bridging the performance gap between CPU and main memory [44]. Research using caching and prefetching in database systems [45, 13, 37, 15] showed that it is important to use applications knowledge to perform caching and prefetching. File caching and prefetching have become standard techniques for sequential file systems [19, 32, 25, 36, 46, 8, 23, 11, 40] ....

Alan J. Smith. Second Bibliography on Cache Memories. Computer Architecture News, 19(4):154--182, June 1991.

....compiler writer and the architect. 1 Introduction Because processor speed is increasingly outpacing memory speed, an enormous amount of research focuses on improving the cache behavior of numerical programs (see for example, Smith s bibliographies on hardware aspects of cache memories [Smi86, Smi91] and compiler techniques that exploit cache memories [CM95, MCT96, LRW91, MLG92, WL91] Most of this work depends on loop nests to provide predictable and regular data accesses. Techniques to improve data cache performance typically target and model locality characteristics found in loop nests. ....

A. J. Smith. Second bibliography on cache memories. Computer Architecture News, 19(4):154--182, June 1991.

....level with CPU registers and includes the on chip and on board caches, the main memory and the hard disk. Cached objects in these levels are uniform size chunks of data, e.g. pages and cache words. The clever management of these caches has been the subject of extensive research in the past decades [13, 14]. The phenomenal growth of the Internet and emergence of distributed information systems, such as the World Wide Web, has necessitated the extension of the cache hierarchy Technical Report WUCS 96 25 y Applied Research Laboratory, Department of Computer Science, Washington University, Campus ....

Allan J. Smith, "Second Bibliography for Cache Memories," Computer Architecture News, Vol. 19, No. 4, June 1991.

....2 Client 1 Server 1 Server 2 Server 3 LAN WAN Figure 1: Web cache caching policies for proxy caches. Most current implementations use traditional memory paging policies like the Least Recently Used (LRU) policy for proxy caching. While LRU has been shown to be very eOEcient for memory caching (see [16, 17] for a survey) this policy is not as good for Web caching, as already reported in several trace driven simulations studies ( 2, 7, 19, 20] This follows from the high heterogeneity of both the Web documents (their size varies from hundreds of bytes to several megabytes) and of the transfer ....

A.J. Smith. Second bibliography for cache memories. Computer Architecture News, 19(4), June 1991.

....[37] 1. 4 Relation to previous work Caching and prefetching have been known techniques to improve performance of storage hierarchies for many years [4, 13] In computer architecture, work on caching and prefetching has focused on bridging the performance gap between processors and main memory [41]. Research using caching and prefetching in database systems [10, 33, 11] showed that it is important to use applications knowledge to perform caching and prefetching. File caching and prefetching have become standard techniques for sequential file systems [13, 28, 20, 31, 42, 5, 18, 6, 36] The ....

Alan J. Smith. Second Bibliography on Cache Memories. Computer Architecture News, 19(4):154--182, June 1991.

....deal with these more general situations [5, 26] 1. 5 Related work Caching and prefetching have been known techniques to improve storage hierarchies for many years [2, 12] In architectures, the work on caching and prefetching has focused on bridging the performance gap between CPU and main memory [29]. Research using caching and prefetching in database systems [9, 23, 10] showed that it is important to use applications knowledge to perform caching and prefetching. File caching and prefetching have become standard techniques for sequential file systems [12, 20, 14, 22, 30, 4, 13, 7, 26] The ....

Alan J. Smith. Second Bibliography on Cache Memories. Computer Architecture News, 19(4):154--182, June 1991.

....simulation are very active research areas due to their inadequate performance rates. In response to this problem, many different computer architecture groups have developed approaches, such as analytic models and novel simulation techniques, for analyzing data in an efficient manner [1] 2] [3]. Analytic cache simulation models can be constructed rather rapidly, but they produce results of dubious accuracy. Therefore, analytic models are inappropriate for prototyping memory systems. The analytic models, however, can be used for other system components, such as processors, where ....

A. J. Smith, "A second bibliography on cache memories," Comput. Architecture News, vol. 19, pp. 138--153, June 1991.

....McKinley, Computer Science Department, LGRC, University of Massachusetts, Amherst MA 01003 4610; email: mckinley cs.umass.edu; O. Temam, Laboratoire PRiSM, Universite de Versailles, 45 Avenue des Etats Unis, 78000 Versailles France; email: temam prism.uvsq.fr. 2 Delta McKinley and Temam ories [Smith 1986; 1991] and compiler techniques that exploit cache memories [Coleman and McKinley 1995; McKinley et al. 1996; Lam et al. 1991; Mowry et al. 1992; Wolf and Lam 1991] Most of this work depends on loop nests to provide predictable and regular data accesses. Techniques to improve data cache performance ....

Smith, A. J. 1991. Second bibliography on cache memories. Computer Architecture News 19, 4 (June), 154--182.

....they travel and other communication link parameters. Also given is the fact that cache space is always limited. Therefore deciding which item(s) to replace when a new one arrives is an important and interesting optimization problem. This problem has been adequately studied in memory paging [10, 11], however with the non uniformity assumption that holds in the network environment it deserves a great deal of new research. In this paper, we present a method of optimally solving the replacement problem. Section II and III present the notations and definition of the problem. In Section IV we ....

Allan J. Smith, "Second Bibliography for Cache Memories," Computer Architecture News, Vol. 19, No. 4, June 1991.

....much better than a naive strategy, both theoretically and in practice. In the systems community, caching and prefetching have been known techniques to improve the performance of storage hierarchies for many years [2, 11] The breadth of application of these techniques has ranged from architecture [29] to database systems [8, 24, 9] to file systems [11, 20, 14, 22, 30, 3, 13, 6, 27] and beyond. A recent trend in this research is to use applications knowledge about their access patterns to perform more effective caching and prefetching [3, 6, 26, 27] Our practical motivation for this problem ....

Alan J. Smith. Second Bibliography on Cache Memories. Computer Architecture News, 19(4):154--182, June 1991.

....hierarchies composed of cache memories are so common and crucial to high performance computer architecture design that performance evaluation of cache memories has received phenomenal attention. In 1991, Smith catalogued 487 technical papers and reports that dealt with some aspect of caching [14]. This section addresses the problem of simulating cache designs before design requirements are known. To do this requires measurement of the performance of a large number of cache designs. This cache performance evaluation process must be fast to be able to use large workloads as inputs. The ....

A. J. Smith, "A second bibliography on cache memories," Comput. Architecture News, vol. 19, pp. 138--153, June 1991.

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A. J. Smith, "Second bibliography for cache memories," Computer Architecture News, vol. 19, no. 4, 1991.

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A. J. Smith, "Second bibliography for cache memories," Computer Architecture News, vol. 19, no. 4, 1991.

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Smith, A. J. 1991. "Second bibliography on cache memories," ACM SIGARCH Computer Architecture News, vol. 19, no 4, pp. 154-182.

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