M. D. Hill. A Case for Direct-Mapped Caches. Computer, 25--40, Dec. 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....memory references, we are aware that data memory references are also an important source of cache conflicts. Thus, it is also worthwhile to optimize the cache placement of data [6,7] 6. 1 Similar code placement techniques Some of the earliest work in this area was done by Hwu and Chang [21], McFarling [26] and Pettis and Hansen [27] Hwu and Chang use a WCG and a proximity heuristic to address the problem of basic block placement. Their approach is unique in that they also perform function inline expansion during code placement to overcome the artificial barriers imposed by ....

M. D. Hill, "A Case for Direct-Mapped Caches." Computer 21, 12, p.25, 1988.

....logic select data 0 . 0 1 . 1 downsize upsize resizing range select data data way0 data array data way n . Size of each way Set associativity 4 way 3 way 2 way dm 4K 16K 12K 8K 4K 2K 8K 6K 4K 2K Table 1: Enhanced resizing granularity using hybrid. formance [5]. Downsizing from a 4 way 32K, our cache opts for a larger 24K size with a lower set associativity of 3 ways rather than selecting a 4 way 16K cache as selective sets would. Such an approach increases the resizing opportunity for applications with working set sizes closer to 24K than 16K. Table ....

M. D. Hill. A case for direct-mapped caches. IEEE Computer, 21(12):25--40, Dec. 1988.

.... Gammad We can now derive the number of misses suffered by a process on its return from a context switch. We will focus on deriving a simple and accurate formula for direct mapped caches. Because they are simple and fast, direct mapped caches are popular with processor architects [10, 11]. In a direct mapped cache (D = 1) a block of process i resident in some cache set is purged if one or more blocks from the intervening processes map to that set. The probability one or more blocks of the intervening processes map to a given cache set is one minus the probability zero blocks of ....

Mark D. Hill. A case for direct-mapped caches. IEEE Computer, 21(12):25 -- 40, December 1988.

....5 discusses performance techniques motivated by the results and insights of Section 4. Finally, Section 6 summarizes and suggests further uses of DTrack. 2 Related Work A common method of producing aggregate memory statistics is through simulation, of which we cite a few representative samples [1, 7, 19, 3]. More sophisticated cache memory behavior analysis tools have been developed [20, 8, 11, 12, 13, 14] and this section compares DTrack to this prior work. Our work di ers from these tools in that we consider pointer data structures in addition to arrays, and show that aggregate statistics obscure ....

M. D. Hill. A case for direct-mapped caches. IEEE Computer, 21(12):25-40, Dec. 1988.

....more important than the small reduction in miss ratio that is achieved through associativity. Recent studies using trace driven simulation methods have demonstrated that direct mapped caches have significant performance advantages over set associative caches for cache sizes of 32K bytes and larger [Hill87, Hill88]. 2.1.3 Previous cache memory research [Smith82] is an excellent survey paper on cache memories. Various design features and tradeoffs of cache memories are discussed in detail. Trace driven simulations are used to provide realistic performance estimates for various implementations. Specific ....

....cache to inform the crosspoint caches of the location (which element in the set) of each line it loads. In future systems, however, direct mapped caches are likely to see more frequent use than set associative caches, since direct mapped caches are significantly faster for large cache sizes [Hill87, Hill88]. 91 MSB Address bits LSB 16 6 4 2 2 2 On chip Tag for Line in Word Byte cache bit on chip on chip in in mapping cache cache line word Crosspoint Tag for Line in Memory Word Byte cache bit crosspoint crosspoint bank in in mapping cache cache select line word Figure 5.7: Address bit ....

MARK D. HILL. "A Case for Direct-Mapped Caches". Computer, volume 21, number 12, December 1988, pages 25--40.

....potentially be performed efficiently for a swap instruction. A direct mapped data cache can send the value to be loaded from memory to the processor for a load or a swap instruction in parallel with the tag check. This value will not be used by the processor if a tag mismatch is later discovered [7]. A data cache is not updated with the value to be stored by a store or a swap instruction until after the tag check [7] Thus, a swap instruction could be performed as efficiently as a store instruction on a machine with a direct mapped data cache. In fact, a swap instruction requires the same ....

....from memory to the processor for a load or a swap instruction in parallel with the tag check. This value will not be used by the processor if a tag mismatch is later discovered [7] A data cache is not updated with the value to be stored by a store or a swap instruction until after the tag check [7]. Thus, a swap instruction could be performed as efficiently as a store instruction on a machine with a direct mapped data cache. In fact, a swap instruction requires the same number of cycles in the pipeline as a store instruction on the MicroSPARC I [10] One should note that a swap instruction ....

M. D. Hill, "A Case for Direct--Mapped Caches," IEEE Computer, 21(11), pp. 25-- 40, December 1988.

....in the caching of a significant number of less recently used lines which are less likely to be re referenced before replacement. Such an effect is especially pronounced for the directmapped cache which, because of its fast access time, is often the cache topology of choice for first level caches [7]. For instance, results from trace driven simulations show that on average, 40 of the cache frames in a direct mapped data cache contain less recently used lines during the execution of the Transaction Processing Performance Council Benchmark C (TPC C) 27] and that such lines have only about 1 ....

....the paper. 2 Underutilized Cache Frames The performance of a cache is determined both by the fraction of memory requests it can satisfy and the speed at which it can satisfy them. The simple direct mapped cache provides a fast access time but tends to have a low hit ratio due to conflict misses [7]. In a direct mapped cache, a line can only be located at a fixed position. This restrictive line placement means that lines that have been assigned the same cache frame have to replace one another, even when they have been referenced very recently. In other words, the direct mapped cache is ....

M. Hill "A Case for Direct-Mapped Caches," IEEE Computer, Vol. 21(12), Dec. 1988, pp. 25--40.

....bridge the gap between the profiling and modeling tools from the two traditionally independent synthesis domains (architecture and CAD) we have developed a new synthesis and evaluation platform. The platform integrate s the existing modeling, profiling (SHADE [Cme94] and simulation (DINEROIII [Hill88] tools with the developed system level synthesis tools. Application profiles are acquired through the use of SHADE controlled by our own trace analyzer. The result of the trace analysis is an application control flow graph augmented with information on spatial and temporal correlation of branch ....

.... Application driven microprocessor design, and its performance issues, have been studied by Fisher et al. Fis96] Energy e#cient microprocessor design has been discussed [Bur96, Gon96] Instruction and data caches, as the highest level of the memory hierarchy, have been thoroughly studied [Smi83, Hill88, Jou93] Various memory hierarchy synthesis techniques for multimedia systems have been developed [Fu96] Cache models for latency [Wil94, Wad92] and power [Ko95, Eva95, Su95] have been developed and power minimization strategies have been evaluated for a number of architectural parameters. Gray ....

M.D. Hill. A case for direct-mapped cache. IEEE Computer, pp. 25-40, 1988.

....efficiently for a swap instruction on most RISC machines. A direct mapped data cache can send the value to be loaded from memory to the processor for a load or a swap instruction in parallel with the tag check. This value will not be used by the processor if a tag mismatch is later discovered [7]. A data cache is not updated with the value to be stored by a store or a swap instruction until after the tag check [7] Thus, a swap instruction could be performed as efficiently as a store instruction on a machine with a direct mapped data cache. In fact, a swap instruction requires the same ....

....from memory to the processor for a load or a swap instruction in parallel with the tag check. This value will not be used by the processor if a tag mismatch is later discovered [7] A data cache is not updated with the value to be stored by a store or a swap instruction until after the tag check [7]. Thus, a swap instruction could be performed as efficiently as a store instruction on a machine with a direct mapped data cache. In fact, a swap instruction requires the same number of cycles in the pipeline as a store instruction on the MicroSPARC I [11] One should note that a swap instruction ....

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M. D. Hill, "A Case for Direct--Mapped Caches," IEEE Computer, 21(11), pp. 25--40 (December 1988).

....also conflict misses (due to a cache set overfilling, even though the cache as a whole may not be full) Particularly for direct mapped caches, conflict misses substantially increase the total miss rate. Nevertheless, direct mapped caches are often implemented, because they are fast. Indeed, Hill [2] argues that the smaller cycle time more than compensates for the greater miss rate, with the result that direct mapped caches may have the lowest average memory access time. Jouppi [4] has proposed victim caching as a simple means of making a fast direct mapped cache even more efficient. A ....

Hill, Mark D., "A Case for Direct-Mapped Caches," Computer, vol. 21, no. 12, pp. 25-- 40, December 1988. Argues that, because of their fast hit-times, direct-mapped caches may often be most efficient.

....access behavior whether the full utilization of high bandwidth improves the system performance or not. Increasing cache associativity is the most major method, assuming the constant cache size, to avoid cache conflicts. However, this approach usually increases the cache access time dramatically[3][12] It is desirable, therefore, to reduce cache conflicts caused by large cache lines without increasing cache associativity. In this section, we propose a novel cache architecture for merged DRAM logic LSIs, called variable line size cache orVLS cache. The VLS cache has a variable line size, ....

Hill, M. D., "A Case for Direct-Mapped Caches," IEEE Computer, vol.21, no.12, pp.25--40, Dec. 1988.

....with the processor. The configuration of the cache is direct mapped with 512 blocks of 32 words each. The direct mapped approach was chosen for several reasons. First, the hit rate for direct mapped caches approaches that of caches with more associativity when the size of the cache becomes large [9]. Second, one side effect of higher degrees of associativity is that the memory must be made wider, since N banks of memory are required to implement N way set associativity. Since the VLIW already requires a fairly wide memory structure, this would merely compound the problem. Finally, the ....

M.D. Hill, "The Case For Direct-Mapped Caches," IEEE Computer, vol. 21, no. 12, pp. 25-41, December 1988. 12 A Captions Captions for Gray, Naylor, Abnous, Bagherzadeh; VIPER -- A VLIW Integer Processor:

....loads. Section 4 describes our performance model. Section 5 shows non vital load analysis while section 6 presents resource impact. Section 7 concludes and details future work. 2. Previous Work The agenda of previous work is to maintain a high hit rate while increasing the speed of the DL1 [8]. The first research used streaming buffers, victim caches [12] alternative cache indexing schemes [17] etc [9] Another approach is to try to achieve free associativity. Calder et al. [5] following the spirit of [11] 10] 2] 15] proposed the predictive sequential associative cache (PSA cache) ....

M. D. Hill. "A Case for Direct-Mapped Caches," IEEE Computer, pp. 25 -- 40, Dec. 1988.

....space, implying modestly associative AM with a corresponding modest amount of unallocated memory may adequately reduce replacement overhead. Although higher associativities have been discouraged in caches because of the increased hit processing time due to increased cache controller complexity [7], COMA seems to f avor them . 6. Conclusion Unallocated memory space is an important design parameter unique to COMA multiprocessors that has not been treated in detail in previous works. In this paper, we have made an initial study of unallocated space and pointed out the critical parameters to ....

Mark D. Hill, "A Case for Direct-Mapped Caches", Computer, pp. 25-40, December, 1988.

....in any of the cache lines. A cache is n way set associative if a given line may reside in only n locations. A cache is direct mapped (or one way set associative) if a given line maps to only one location. Providing associativity increases hardware costs and increases the access time of the caches [Hil88] The cache access time is typically the cycle time limiter, so increasing the cache access time increases the processor cycle time, thereby reducing performance. Compulsory misses are due to the first access to a memory location (that maps to a cache line) since the first access will not be in ....

....since they are physically bigger and hence further away from the processor (even when on chip) In addition, the decoder is bigger and hence slower. Another way to reduce the miss rate is to CHAPTER 2. DATA BANDWIDTH PROBLEMS 16 add associativity, however associativity increases access time [Hil88] To obtain a cache with a low miss rate, the cache size and associativity must be increased. However, this increases the latency of a cache access. Since the cache access is a critical path in many processors, the cycle time of those processors has to increase. Sometimes this tradeoff ....

Mark Hill. The Case for Direct-Mapped Caches. IEEE Computer, 21(12):25--40, December 1988.

.... la consistence des donn ees dans le cache) Mots cl e : cache, temps d acc es, taux d echec, indexage virtuel, consistence de cache DASC cache: dealing with cache access time and virtual indexing 1 1 Introduction In a microprocessor, the cache hit time generally determines the clock frequency [6]. But for the ten last years, a technological trend is the increase of the cache miss penalty in terms of instruction issue delays; then maintaining the cache miss ratio as low as possible is also of particular interest [10] For a few years, there has been numerous propositions of structures for ....

....7 summarizes this study. 2 Andr e Seznec 2 Conjugatind low cache hit time and low cache miss ratio In this section, we recall some previous propositions of cache structures for allowing low cache hit time and low cache miss ratio. In this paper, we shall adopt the same definitions as Hill in [6]: Definition 2.1 The cache hit time H c is the delay for getting back a data from the cache on a hit. Definition 2.2 The cache access time A c is the average delay for getting back a data from the cache. A rough modelization of the cache access time is: A c = H c miss P enalty (1) where ....

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M.D. Hill, "A case for direct-mapped caches", IEEE Computer, Dec 1988

....the previously described functions f i i.e. a very few XOR gates. 3 Semi unified caches The major argument that is advanced for using direct mapped caches rather than set (or skewed) associative caches is a shorter cache hit time (i.e. the delay for accessing a data in the cache on a hit) [8]. A cache read on a direct mapped cache may be decomposed into two consecutive steps: 1. Read the word and associated tags in cache 2. Check the tags against the address of the data While a cache read on a n way set associative cache consists in three consecutive steps: 1. Read a set of n ....

....a request on a semi unified cache The sequencing of an instruction request at address A is as follows: 1. the request is presented to the I cache : 2. on a miss, the request is presented to the D cache. From now, this first level cache miss is called an on chip miss: 1 2 was reported by Hill [8] 2 Notice that optimistic execution is also possible with a set associative cache [4] but at a significantly higher implementation cost. RR n2083 8 Nathalie Drach, Alain Gefflaut, Philippe Joubert, Andr e Seznec ffl On a hit in the data cache, the requested line is brought back in the ....

M.D. Hill, "A case for direct-mapped caches", IEEE Computer, Dec 1988

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M. D. Hill. A Case for Direct-Mapped Caches. Computer, 25--40, Dec. 1988.

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M. Hill "A Case for Direct-Mapped Caches," IEEE Computer, Vol. 21(12), Dec. 1988, pp. 25--40.

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M. D. Hill. A case for direct-mapped caches. IEEE Computer, 21(12):25--40, December 1988.

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M. D. Hill. A case for direct mapped caches. In IEEE Computer. IEEE Computer Science Press, 1988. 11

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M. D. Hill. A case for direct-mapped caches. IEEE Computer, 21(12):25--40, Dec. 1988.

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Mark D. Hill. A case for direct-mapped caches. IEEE Computer, 21(12):25--40, December 1988.

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Mark D. Hill, "A Case for Direct-Mapped Caches," IEEE COMPUTER, pp.25-40, December 1988

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M. D. Hill, A Case for Direct-Mapped Caches, IEEE Computer 21(12), 1988, pp. 25-40.

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