J. Bormann, J. Lohse, M. Payer and G. Venzl, "Model Checking in Industrial Hardware Design", DAC'95, pp. 298-303.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....problems. All of these case studies were done by formal verification experts, rather than by designers. RuleBase s intention is to make model checking accessible to the general design community. Two model checking tools that have been published in the past year are Verdict [PP95] and CVE [BLPV95]. Both are integrated into the design environment in the sense that they accept standard languages (Verilog and VHDL, respectively) Verdict, like RuleBase, is based on SMV, while CVE has an independent model checker. It is difficult to compare capacity without the aid of a benchmark, thus we can ....

J. Bormann, J. Lohse, M. Payer and G. Venzl, "Model Checking in Industrial Hardware Design", DAC'95, pp. 298-303.

....way of finding errors in software systems. Testing, however, can be very expensive, but more importantly, it is often incapable of finding subtle errors e.g. timing errors in a concurrent system. Model checking has been used extensively to find subtle errors in hardware and protocol designs [BLPV95,CW96,Hol91] However, until recently, model checking has been deemed inadequate to analyze software code, due to the high level of detail often found in code. Now there are many groups, from both industry and academia, that are analyzing source code by model checking. Many of these source code ....

J. Bormann, J. Lohse, M. Payer, and G. Venzl. Model checking in industrial hardware design. In Proc. of the 32nd Design Automation Conference, 1995.

....state machine from an HDL based description has become an important aspect of the current generation of language based design methodologies. Such techniques have application in numerous areas: in formal verification when establishing the behavioral equivalence of two system descriptions (c.f. [5] [17] in synthesis when the implementations in hardware or software must be faithful to the behavior of the language based specification (c.f. 4] 9] and in high performance simulation when cycle level approximations are used (c.f. 22] The current generation of HDLs are based on the ....

....To date, there has been no theory which explains how behaviors defined by discrete event models relate to the computational model of hardware: finite state machines. Existing approaches have applied ad hoc style guidelines in an effort to constrain the problem for synthesis or verification (c.f. [5] [8] 10] 19] 20] Such proposals have met with mixed success since all are different and all are justified by the idiosyncratic needs of a particular user community or design tool. What is needed is a general theory which addresses the behavioral extraction problem at the semantic level and ....

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J. Bormann, J. Lohse, M. Payer and G. Venzl, "Model Checking in Industrial Hardware Design," In Proc. of 32nd DAC, June 1995, pp 298-303.

....studies, with verification results. Discussions and conclusions are given in Section 5 and Section 6, respectively. 2. MODEL CHECKER AND LANGUAGE We used SMV [1] as our model checker because it has many good features to support real designs and there are many success stories from the industry [2][3][4] 5] 6] 7] SMV supports various features to reduce the problem size, i.e. the scalarset data type for symmetric reduction, the ordset data type for induction, the subclass structure for case splitting, the layer structure for the compositional assume guarantee verification, and the property ....

J. Bormann, J. Lohse, M. Payer, and G. Venzl, "Model Checking in Industrial Hardware Design," in 32nd DAC, pp. 298-303, 1995.

....way of finding errors in software systems. Testing, however, can be very expensive, but more importantly, it is often incapable of finding subtle errors e.g. timing errors in a concurrent system. Model checking has been used extensively to find subtle errors in hardware and protocol designs [BLPV95] CW96] Hol91] However, until recently,modelchecking has been deemed inadequate to analyze software code, due to the high level of detail often found in code. Now there are many groups, from both industry and academia, that are analyzing source code by model checking. Many of these source code ....

J. Bormann, J. Lohse, M. Payer, and G. Venzl. Model checking in industrial hardware design. In Proc. of the 32nd Design Automation Conference, 1995.

....of some properties of the following types : safety, liveness, and bounded time safety. The latter type involves reasoning on quantitative time. As the size of the considered system was too large for a global handling of some of the proofs by the SVE BDD tool (Siemens Verification Engine [30, 31, 32, 33]) system verification was performed, cf. section 3.1. In this way, the requested properties were verified, in a modular way. Interestingly enough, one property was found which could possibly be violated by the design, this was due to the inadequate handling of a very unlikely configuration for ....

....large, complex systems Both component and system verification have been addressed in SACRES. Component verification consists in checking properties for a monolithic software component considered as a whole. Our technology basis for component verification is a BDD package developed at Siemens [30, 31, 32, 33]. While modern BDD packages are extremely powerful and optimized, their processing capabilities is still below what is frequently requested for verifying software for embedded systems. Two answers can be considered to meet this challenge of complexity : 1. Usually, software for verification was ....

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J. Bormann, J. Lohse, M. Payer and G. Venzl. Model Checking in Industrial Hardware Design. Proceedings 32nd Design Automation Conference, June 1995.

.... of California at Berkeley and the University of Colorado at Boulder unifies the mentioned verification techniques for finite state machines and techniques for synthesis of VLSI circuits [8] Meanwhile, there are also commercial systems, e.g. CVE (Circuit Verification Environment) by Siemens [5], or the system RuleBase by IBM [2] which is built on top of SMV. 6 Variants and Extensions of OBDDs For further improving the efficiency of the data structures, several variants and extensions of OBDDs have been proposed. For some specific application fields, these refined models are better ....

J. Bormann, J. Lohse, M. Payer, and G. Venzl. Model checking in industrial hardware design. In Proc. 32nd ACM/IEEE Design Automation Conference (San Francisco, CA), pages 298--303, 1995.

.... with identical state encodings can be compared in the commercial verifier VFORMAL [27] More recently, another approach close to ours for synchronous circuits has been published [28] Cycle level synchronization semantics of VHDL [16, 40] serve as a basis for Siemens verification environment CVE [41] and a model checking system under development at Carnegie Mellon University [29] Models based on Petri Nets [30,31] tend to create an excessively large number of states, and a phase of state space reduction is required before model checking tools are applied. The semantic definition of a VHDL ....

J. Bormann, J.Lohse, M. Payer and G.Venzl: "Model Checking in Industrial Hardware Design", Proc of DAC' 95.

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