Texas Instruments. SuperSPARC User's Guide, volume SPKU005. Texas Instruments, October 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....mechanisms in the processors are not assumed for the above techniques, and they are thus applicable to all computers. The following mechanisms are useful for the high speed implementation of the MBCF, and take advantage of special features of the latest, most advanced processors (e.g. SuperSPARC [24, 67] and UltraSPARC [70, 81] ffl TLB corresponding to coexistence of multiple contexts Each entry in the translation look aside buffer (TLB) of a recent processor has a field for a context identifier (context ID) and the OS for the processor can switch contexts without clearing entries from the ....

....copies of data must be generated in an MPSI than in an MBCF. To make the best use of its flexibility, the MBCF system makes direct accesses to user spaces from the interrupt routine (in kernel mode) However, as described in Section 5. 1, high end processors in recent times (such as SuperSPARC [24] or UltraSPARC [70] include the following mechanisms for realizing memoryaccess to user spaces from the kernel space without incurring penalties. ffl The processor is able to change the current task space (context) without purging all TLB entries. ffl Many pages from various task spaces can ....

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Texas Instruments. SuperSPARC User's Guide, volume SPKU005. Texas Instruments, October 1992.

....and 4 cycles on the SuperSPARC and UltraSPARC. Blocks with a single instrumented single exit predecessor or a single instrumented single entry successor are not instrumented. The SuperSPARC and hyperSPARC experiments ran on dual processor Sun SPARCstation 20s equipped with 55Mhz SUN SuperSPARC [16] processors and 66Mhz ROSS hyperSPARC processors [13] Both systems ran Solaris 2.4. The UltraSPARC experiments ran on a SPARCstation 140 with a 143Mhz SUN UltraSPARC processor [15] running Solaris 2.5. The test programs were compiled O (not at SPEC optimization levels) by the Sun C and Fortran ....

Texas Instruments. SuperSPARC User's Guide, October 1993.

.... that the processor does have means to directly control the cache tags by issuing two instructions: invalidate and flush (downgrade to read only) For our SPARC based platform these two instructions are implemented as loads from the untranslated physical block address in special alternate spaces [76]. These alternate spaces are recognized by the cache controller which carries out the downgrade autonomously. 3.3.2 System Integration of the Coherence Handlers Sub Kernel Coherence Handlers Implementing shared memory in software raises the problem of choosing the level where the coherence ....

....with the application or with the simulator by simply modifying some macros. The former case corresponds to hybrid DSM systems. In the latter case, we simulate an ideal hardware implementation where protocol handlers take zero time to execute. 51 The processor simulator is an efficient SPARC V8 [76] interpreter with a throughput of 1.2 MIPS on a Ultra Enterprise 3000 host equipped with a 168MHz UltraSPARC CPU. The processor simulator features trapping on exceptions raised by the simulated memory through the MEXC line. Traps are generated for over flows and under flows of the eight register ....

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Texas Instruments. SuperSPARC User's Guide. October 1992.

....execute in 4 cycles on both SuperSPARC and UltraSPARC processors. Blocks with a single instrumented single exit predecessor or a single instrumented singleentry successor are not instrumented. The SuperSPARC experiments ran on dual processor Sun SPARCstation 20 equipped with 50Mhz SUN SuperSPARC [17] processors, running Solaris 2.4. The UltraSPARC experiments ran on an 12 slot Ultra Enterprise 4000 5000 with 167Mhz Sun E E E Benchmark Avg. BB Size Uninst. Time Inst. Time Sched. Time Hidden 099.go 2.9 739.2 1830.7 (2.48) 1582.4 (2.14) 22.7 124.m88ksim 2.2 432.8 1208.2 (2.79) 1081.4 ....

Texas Instruments. SuperSPARC User's Guide, October

....This seems excessively pessimistic given that the host machine a SPARCstation 10 51 has a unified 1 megabyte direct mapped second level cache backing up the 16 kilobyte 4 way associative first level data cache. Instead, I assume C hostmiss is the first level cache miss penalty, or 5 cycles [76]. To validate this model, I use 4 programs from the SPEC92 benchmark suite [70] compress, fpppp, tomcatv, and xlisp. All programs operate on the SPEC input files, and are compiled with gcc version 2.6.0 or f77 version 1.4 at optimization level O4. Program characteristics are shown in Table 3. To ....

....is the only benchmark with a non negligible instruction cache miss ratio (3.7 ) and predicts the number of instruction cache misses within 15 for Fast Cache and 10 for Fast Cache Indirect. To further evaluate this model I use the reference counter of the SuperSPARC second level cache controller [76] to measure the number of level one misses for the original data set. The count includes both data cache read misses and instruction cache misses, but fpppp is dominated by instruction cache misses. predicts the number of misses within 36 for Fast Cache and 4 for Fast CacheIndirect. 2.6.3 ....

Texas Instruments. SuperSPARC User's Guide, 1992. Alpha Edition.

....This seems excessively pessimistic given that the host machine a SPARCstation 10 51 has a unified 1 megabyte directmapped second level cache backing up the 16 kilobyte 4 way associative first level data cache. Instead, we assume C hostmiss is the first level cache miss penalty, or 5 cycles [32]. The characteristics of the programs used to validate this model are shown in Table 3. Figure 13 plots the measured and modeled slowdowns as a function of target miss ratio. The lowest line is Slowdown Inst , the asymptotic lower bound. The upper C lookup f cc C cc 1 f cc ( C nocc ....

....is the only benchmark with a non negligible instruction cache miss ratio (3.7 ) and predicts the number of instruction cache misses within 15 for Fast Cache and 10 for Fast Cache Indirect. To further evaluate this model we use the reference counter of the SuperSPARC second level cache controller [32] to measure the number of level one misses for the original data set. The count includes both data cache read misses and instruction cache misses, but fpppp is dominated by instruction cache misses. predicts the number of misses within 36 for Fast Cache and 4 for Fast Cache Indirect. 6.3 Overall ....

Texas Instruments. SuperSPARC User's Guide, 1992. Alpha Edition.

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Texas Instruments. SuperSPARC User's Guide, volume SPKU005. Texas Instruments, October 1992.

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