Eric A. Brewer. Aspects of a parallel-architecture simulator. MIT/LCS 527, Massachusetts Institute of Technology, February 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....to its simulation capabilities, Proteus also provides a rich set of measurement and visualization tools that facilitate debugging and monitoring. Most of the graphs included in this report were produced directly by Proteus. Proteus has been shown to accurately model a variety of multiprocessors [Bre92] but the purpose of our simulations was not to model a specific multiprocessor architecture. Rather, it was to adjust key parameters of multiprocessors such as messaging overhead and network transmission delay to allow us to develop an analytic model that could be applied to many architectures. ....

E. Brewer. Aspects of a Parallel-Architecture Simulator. Technical Report TR-527, MIT, 1992.

....executed on a simulator of a hypothetical FUNet system. We first describe the simulator to establish confidence in the results of the experiments. Next, we explain the two benchmark programs and analyze the results of the simulations. 5. 1 The FUNi Simulator The simulator is based on the PROTEUS [4] simulation engine that allows rapid development of event driven simulators of parallel architectures. The PROTEUS simulation engine is a collection of C source files for an abstracted core system of a simulator. The FUNet simulator is created by incorporating a custom simulation of FUNi and FUNet ....

E. A. Brewer. Aspects of a parallel-architecture simulator. Technical Report MIT/LCS/TR-527, Laboratory of Computer Science, Massachusetts Institute of Technology, January 1992.

....the application is automatically transformed into a sequential program. This program will simulate all events that would have occurred on the target machine during a real run of the application. The result of the simulation can be examined with the appropriate tools. Among them are: Prot eus [3] : This tool allows for quite a realistic simulation. First, at compiletime the cost of each basic block of the application is evaluated to be able to take it into account during the simulation. Then the application is sequentially simulated with a simulation engine, which is responsible for: ....

E. A. Brewer. Aspects of a parallel-architecture simulator. Technical Report MIT/LCS/TR-527, Massachusetts Institute of Technology, Laboratory of Computer Science, February 1992.

....from it. Indeed, it is possible to reduce the number of transfers by specifying [BLOCK] as the distribution for all three arrays. In this case, elements A[0 : 1; 0 : 7] are owned by processor [0] A[2 : 3; 0 : 7] belong to processor [1] A[4 : 5; 0 : 7] to processor [2], and A[6 : 7; 0 : 7] to processor [3] To observe the effect of this change on the communication volume, the programmer can call the communication statistics display described below. 2.2.4 Communication Statistics Display. The programmer can generally enhance a program s performance by ....

....was chosen over cycle by cycle simulation because even though it is not as accurate, it is a lot faster and better suited to the user s need. We believe that it is a good compromise between speed and accuracy. This compiled simulation was first used in Threads [13] and perfected by Proteus [4, 2], our simulator s predecessor. 5.2 Performance Debugging Using the Simulator The simulator is made of two major components: 1. Code augmenter. This module is part of the C compiler and provides a simulated clock during the execution of the simulated program. 2. Simulation engine. It allows the ....

E. A. Brewer. Aspects of a parallel architecture simulator. Technical Report MIT/LCS/TR527 (Master's Thesis), Massachusetts Institute of Technology, January 1992.

....of only 100. The simulator is event driven (as opposed to cycle per cycle simulation) we use software processes (as opposed to Unix) and we use code augmentation and compile time simulation [21] to account for the timing of programs. Our technique was inspired by the Proteus simulator from MIT [4, 3]. We encourage the use of our simulator. It provides many advantages over running directly on a multiprocessor, including versatility, trivial repeatability and detailed nonintrusive performance debugging and functional debugging. A simulator is more versatile, it can easily simulate a wide range ....

E. A. Brewer. Aspects of a parallel architecture simulator. Technical Report MIT/LCS/TR-527 (Master's Thesis), Massachusetts Institute of Technology, January 1992.

....the processor running the simulator executable. The execution time of the computations is modeled using a technique called code augmentation (as described by [10] With code augmentation instructions are added to the application code in order to time the code. Contrary to the PROTEUS simulator [11] that uses a separate program to augment the assembler output file, PARSE has code augmentation implemented at the compiler level. The GNU C C compiler has been modified to produce augmented code when its basic block profiling switch is enabled. The current implemented augmentation assumes that ....

Eric A. Brewer. Aspects of a Parallel-Architecture Simulator. Technical Report MIT/CS/TR-527, MIT, February 1992.

....host is produced. The code for the simulation host is then executed to obtain performance results. In this paper, we will concentrate on the simulation aspects of the EPPP project. First, we will briefly review some existing simulators, in particular, we will examine the Proteus simulator [1, 2, 3] from MIT in detail. Then, we will give more details of our simulator which is based on the Proteus framework. Our simulator will advance the Proteus work by allowing architectures with different instruction sets to be more accurately simulated. Furthermore, our simulator is also tightly ....

E.A. Brewer, "Aspects of a Parallel-Architecture Simulator," Technical Report MIT/LCS/TR-527 (Master's Thesis), Massachusetts Institute of Technology, January 1992.

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Eric A. Brewer. Aspects of a parallel-architecture simulator. MIT/LCS 527, Massachusetts Institute of Technology, February 1992.

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