R. E. Bryant. A methodology for hardware verification based on logic simulation. Journal of the ACM, 38(2):299--328, April 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....quickly confirms that bits are demultiplexed to the correct positions. Using auxiliary variables to tag these bits raises the level of confidence even higher. Extending this approach even further, Bryant has recently described how simulation can be used as a part of formal verification [Bry91] ffl The formal specification may be incomplete. For example, no liveness properties were verified for STARI. Other important issues that are beyond the scope of current formal techniques include power consumption, noise immunity, and manufacturing yield. ffl The formal specification may not ....

Randal E. Bryant. A methodology for hardware verification based on logic simulation. Journal of the ACM, 38(2):299--328, April 1991.

....to the other. A path through the CFG is called a trace and represents one possible flow of control through the program. For our simple example, the CFG is as follows: msm bge mov add 2. 3 Symbolic Simulation Symbolic simulation has become a standard technique in hardware verification (e.g. [5, 4]) although the general concept was originally proposed for software. The basic idea for verifying digital circuits is that rather than simulating a circuit for a particular input vector, we can simulate it with symbolic variables at the inputs and compute the circuit behavior as a Boolean ....

Randal E. Bryant. A methodology for hardware verification based on logic simulation. Journal of the ACM, 38(2):299--328, April 1991.

....I will not address the companion problem of timing verification, for which modern techniques (e.g. 10] can guarantee correctness. No such guarantee is (as yet) possible in establishing the logical correctness of a complex system, although some progress has been made with simple designs (e.g. [2, 8]) So the term simulation in this paper will mean logical simulation only. There are two fundamental challenges to the effective simulation of complex computer hardware. First is the challenge of speed: simulations are orders of magnitude slower than real hardware, so it is extremely important ....

....capable of verifying big systems, or to have rigorous testing regimes that could certify correctness. We can certainly hope that the increasing use of logic synthesis techniques [14] will result in designs with fewer bugs. We can also hope that hardware verification methods of various kinds [2, 8] will be able to handle ever larger and more complex structures. But for the present, simulation is our lot, and we need to do it well. 16 ....

Bryant, R.E. A Methodology for Hardware Verification Based on Logic Simulation. Tech. Report CMU-CS-87-128, Computer Science Dept., Carnegie-Mellon University, June 8, 1987.

....83] discusses the comparison of designs, expressed in a HDL, using conventional symbolic simulation. The practicality of such symbolic simulation was very limited at the time. Bryant s introduction of reduced, ordered BDDs for symbolic switch level simulation [40, 41] for circuit verification [42, 52, 47] renewed interest in symbolic execution; Bryant and colleagues have verified some simple circuits [45, 46, 15] Reeves [205] also constructed a symbolic verifier based on these techniques. Huet al... 135] describe a system for translating a higher level specification notation into low level BDDs, ....

Randal E. Bryant. A methodology for hardware verification based on logic simulation. Technical report CMU--CS--87--128. Computer Science Department, Carnegie-Mellon University, Pittsburgh, PA, June 1987. Published as

....83] discusses the comparison of designs, expressed in a HDL, using conventional symbolic simulation. The practicality of such symbolic simulation was very limited at the time. Bryant s introduction of reduced, ordered BDDs for symbolic switch level simulation [40, 41] for circuit verification [42, 52, 47] renewed interest in symbolic execution; Bryant and colleagues have verified some simple circuits [45, 46, 15] Reeves [205] also constructed a symbolic verifier based on these techniques. Huet al... 135] describe a system for translating a higher level specification notation into low level BDDs, ....

....to compare state machines. Symbolic indexing was introduced in [15] and has been generalized by Hu and colleagues [135] An initial formulation of trajectory evaluation [57] has been used previously to verify stacks, memories, and simple pipelines including a data path and an accumulator [47]. Both pipelines bypassed the read after write hazard. A more complete formulation is in progress [212] The present work is the first application of trajectory evaluation to a large pre existing circuit. 7.7 Chapter summary This chapter has discussed several issues related to the application of ....

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Randal E. Bryant. A methodology for hardware verification based on logic simulation. Journal of the ACM, April 1991.

....( D L T ( T L D ( L T ( T i L T ( L T i ( i = L D ( L T i ( L D ( L T ( T T i T D D R T T R L D R ( L T R ( L D ( L T ( T D R D D R D 12 1.4. 4 Symbolic Simulation In the past, ternary simulation has been used to verify circuits[9][10]. Assuming a monotone excitation function, the simulation algorithm can ensure that any binary values resulting from simulating patterns containing X s would also result when the X s are replaced by any combination of 0 s and 1 s. Thus the number of patterns that must be simulated to verify a ....

R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation," J. ACM, Vol. 38, No. 2, pp. 299-328, April 1991.

....main memory, a performance improvement of more than a factor of 1000 can be achieved. Supported by Motorola Grant y Supported by Micro Grant 1 Introduction The manipulation of very large binary decision diagrams 1 (BDDs) 1, 5] is the key to success for BDD based algorithms for simulation [6], synthesis [8, 15] and verification [3, 7, 11] of integrated circuits and systems. Conventional BDD algorithms are based on a recursive formulation that leads to a depth first traversal of the directed acyclic graphs representing the operand BDDs. A typical recursive depth first BDD algorithm is ....

R. Bryant. A methodology for hardware verification based on logic simulation. Journal of the Association for Computing Machinery, 38(2):299--328, Apr. 1991.

....and the variable order used. For pathologicalexamples like multipliers, even 16 bits is too big to handle. Typically, circuits with up to a few hundred primary inputs can often be verified. For larger circuits, more sophisticated methods are needed. B. Symbolic Simulation Symbolic simulation [4] is a combination of the preceding ideas with conventional logic simulation. The advantage of a conventional logic simulator is accuracy. Detailed timing models, hazards, and oscillatory behavior can all be simulated. The disadvantage of a conventional logic simulator is that only one simulation ....

R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation," J. of the ACM, Vol. 38, No. 2, Apr. 1991, pp. 299--328.

....is compact for many functions encountered in practice. The canonicity and compactness properties of the BDD led to its widespread usage in the area of logic synthesis and testing. The application of BDD is further extended with its use in symbolic computation, which include symbolic simulation [6], reachability analysis [8, 15] and BDD based formal design verification [4, 7, 11] However the BDD representation suffers from the drawback that the size of a BDD required to represent a complex logic circuit is very large. This results in large computation and memory requirements. These ....

R. Bryant. A methodology for hardware verification based on logic simulation. Journal of the Association for Computing Machinery, 38(2):299--328, Apr. 1991.

....if the replacement of the binary value of any bit p j , j = f1; 2; ng, by X generates a new pattern P1 which is not a Gate Sensitive Pattern (NonSensitive Pattern) for gate G. Pi The concept of the force weakness of test patterns based upon their information content was first presented in [17]. 5. The Diagnostic Routine Theorem 1 shows the power of the test pattern pairs generated by the method explained in the previous section, when combined with the Diagnosis by Backward Propagation. The theorem is presented first for tree structured circuits, and then it is generalized. Theorem ....

R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation," Journal of the ACM, Vol. 38, N0. 2, pp. 299-328, April 1991.

....to a factor of 100 can be achieved. 1 Introduction The manipulation of very large binary decision diagrams (BDDs) 1] for BDD related terminology, please refer to [2] is the key to success for BDD based algorithms for simulation, synthesis, and verification of integrated circuits and systems [3]. Conventional BDD algorithms are based on a recursive formulation that leads to a depth first traversal of the directed acyclic graphs representing the operand BDDs. A typical recursive depth first BDD algorithm is shown in Figure 1. The depth first traversal visits the nodes of the operand BDDs ....

R. Bryant, "A methodology for hardware verification based on logic simulation," Journal of the Association for Computing Machinery, vol. 38, pp. 299--328, Apr. 1991.

....the author and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. government. On the other hand, verification of non parametric circuits has been successfully performed by various techniques based on symbolic manipulationof Boolean functions [1, 4, 5, 6, 8, 10, 11, 18]. The success of these techniques is largely due to the availability of automatic symbolic Boolean manipulation algorithms (using canonical Boolean function representations) that are efficient in practice [3, 4] There have been some recent efforts in applying these techniques for iterative ....

R. E. Bryant. A methodology for hardware verification based on logic simulation. Technical Report CMU-CS-87-128, Computer Science Department, Carnegie Mellon University, Pittsburgh, PA, June 1987.

....test patterns is very time consuming because of the large number of patterns required. On the other hand equation solving is much more complex than the methods based on test patterns. Another solution, which is presented here, is to make use of ternary test patterns. These patterns were used in [6], where the theoretical foundations of the formal verification using 3 value simulation were established. Under the application of these patterns the internal signal values are extracted easily, and can then be exploited for the diagnosis. In the method presented in this report, the circuit ....

....against any type of design error. Second, they can be used also for the diagnosis and error localisation under certain error hypotheses. The main concept used is the concept of partial ordering of ternary vectors according to their information content. This concept has been presented in [6] and it states that for the ternary values f 0 , 1 , X g 0 X 0 0 0 0 , 0 X 0 0 1 0 . 0 0 0 and 0 1 0 are the normal Boolean values and 0 X 0 means shouldn t care . If the value of an input i doesn t affect the circuit output under the application of one test ....

R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation", Journal of the Association for Computing Machinery, Vol. 38, N0. 2, pp. 299-328, April 1991.

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R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation," J.ACM, Vol. 38, No. 2 (April, 1991), pp. 299--328.

No context found.

Bryant, R. E. A methodology for hardware verification based on logic simulation. Technical Report CMU-CS-87-128, Carnegie Mellon University, June, 1987.

No context found.

R. E. Bryant, A methodology for hardware verification based on logic simulation, Technical Report CMU-CS-87-128, Carnegie Mellon University, June, 1987.

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R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation," J.ACM, Vol. 38, No. 2 (April, 1991), pp. 299--328.

....run of the trajectory evaluator models the system behavior over a single state sequence, although this sequence is both symbolic and partially ordered. 1. 1 Partially Ordered System Modeling In earlier work, we demonstrated the utility of ternary modeling for verifying a variety of circuits [9, 10]. Our methodology was based on ternary simulation of VLSI circuits, where a third value X is added to the set f0; 1g of possible signal values, indicating an unknown or indeterminate logic value. Assuming a monotonicity property of the simulation algorithm, one can ensure that any binary (i.e. 0 ....

R. E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation," J.ACM, Vol. 38, No. 2 (April, 1991), pp. 299--328.

No context found.

R. E. Bryant. A methodology for hardware verification based on logic simulation. Journal of the ACM, 38(2):299--328, April 1991.

No context found.

Randal E. Bryant. A methodology for hardware verification based on logic simulation. Technical Report CMU-CS-90-122, Computer Science, Carnegie Mellon University, March 1990. Accepted for publication in the JACM.

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Randal E. Bryant. A methodology for hardware verification based on logic simulation. Journal of the ACM (JACM), 38(2):299--328, 1991.

No context found.

Randal E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation", Carnegie-Mellon University Technical Report CMUCS -90-122. March 1990.

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