J. Rabaeg and M. Potkonjak, "Resource. Driven Synthesis in the Hyper system," Proc. Symp. Circuits and Systems, 7ol. 4, IEEE Press, New York, 1990, pp. 2592-  Home/Search   Document Not in Database   Summary   Related Articles   Check

....problem which behaves like a real life design examples during synthesis. The underlying computational model for synthetic design examples is the synchronous data flow graph (SDFG) on semi infinite streams of data [LP95] A design example is specified using a control data flow graph (CDFG) format [RP90]. Other underlying assumptions about the available design examples are the following. The available pool of design examples is reasonably complete in the sense that any new design example of interest is similar to at least one of the design examples already included in the pool of design ....

J. Rabaey and M. Potkonjak. Resource driven synthesis in the hyper system. In

....represented by a data flow graph (DFG) McFa90] Although high level synthesis systems in general are either time or resource constrained, a number of systems become both time and resource constrained along the synthesis trajectory. Examples are the initially time constrained systems HYPER [Raba90], MSSR [Ishi91] TBS [Rama91] CADDY [Gutb92] and NEAT [Timm93] Furthermore, resource constrained IP schedulers based on node packing [Gebo92] also need an upper time bound. All these systems use execution intervals (EIs) to identify the cycle steps in which operations can be scheduled. They only ....

J. Rabaey and M. Potkonjak, "Resource Driven Synthesis in the HYPER System", Proc. ISCAS--90, pp. 2592--2595, 1990.

....design is an artificially generated instance of a synthesis problem. The underlying computational model for synthetic design examples is the synchronous data flow graph (SDFG) on semi infinite streams of data [12] A design example is represented by a control data flow graph (CDFG) format [13]. Also assumed is that the available pool of design examples, which is used to characterize design space, is reasonably complete in the sense that any new design example of interest is similar to at least one of the design examples already included in the pool of design examples in its diversity ....

J. Rabaey and M. Potkonjak. Resource driven synthesis in the HYPER system. In 1990 IEEE International Symposium on Circuits and Systems, volume 4, New Orleans, LA, USA, May 1990.

....we used the synchronous data flow graph (SDFG) on semi infinite streams of data [13] as the underlying computational model for synthetic benchmarks since we had a large number of design examples based on the model. A design example is represented by a control data flow graph (CDFG) format [14]. Also assumed is that the available pool of design examples, which is used to characterize design space, is reasonably complete in the sense that any new design example of interest is similar to at least one of the design examples already included in the pool of design examples in its diversity ....

J. Rabaey and M. Potkonjak. Resource driven synthesis in the HYPER system. In 1990 IEEE International Symposium on Circuits and Systems, volume 4, New Orleans, LA, USA, May 1990.

....tasks are decoupled and solved independently. The disadvantage of the approach is that it could yield sub optimal results since decisions chosen in one phase can have significant negative impact on the results obtained in another. In another approach, for example the approach taken in hyper [98, 99], a global optimization routine simultaneously takes into consideration all these tasks. Here the problem is harder than the previous one. A decision was made to adopt this type of approach mainly because of the availability of the installed hyper software base, and the potential for superior ....

J. Rabaey and M. Potkonjak. "Resource Driven Synthesis in the HYPER System". ISCAS, 1990. BIBLIOGRAPHY 173

....structures and function hierarchy. In order to arrive at efficient synthesis results, it has been recognized that transformations on algorithm specifications are crucial. Up to now this issue has been investigated mainly for data flow transformations on scalar processing, as in digital filters [6, 15, 19]. We claim however that these transformations are even more crucial in the presence of M D signals. Indeed, studies on memory organization for M D signals [8, 26] have shown that, for instance, loop transformations can have effects that influence implementation costs in the order of several ....

....ffl = available, ffi = partially available Table 1: Comparision of model features for M D RSP. As a summary, in table 1, the model requirements from section 2 are related to the models that have been developed in different domains. It also includes a comparison with the ubiquitous CDFG model [10, 4, 19], which is typically used in synthesis of multiplexed architectures for scheduling and allocation purposes of scalar data flow and conditional control flow. In our approach, the emphasis lies on exactness, both for having available all individual dependencies like for non array type signals, but ....

J. Rabaey, M. Potkonjak, "Resource Driven Synthesis in the Hyper system," IEEE Int. Symposium on Circuits and Systems(ISCAS-90), Vol. 4, New Orleans, (LA, USA), pp. 25922595, May 1990.

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J. Rabaeg and M. Potkonjak, "Resource. Driven Synthesis in the Hyper system," Proc. Symp. Circuits and Systems, 7ol. 4, IEEE Press, New York, 1990, pp. 2592-

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J. Rabaey, M. Potkonjak, Resource Driven Synthesis in the HYPER System, IEEE ?, 1990

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J. Rabaey and M. Potkonjak, "Resource driven synthesis in the HYPER system," in Proc. of the IEEE Int. Symp. Circuits and Systems, 1990, pp. 2592--2595.

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