R. Ernst and W. Ye, "Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification", Proc. Int. Conf. on CAD, 1997, pp. 598-604.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....a simulation of the program, and hence can provide conservative worst case execution time information. However, so far it has been applied only to single programs, and not to multi tasking environments common in embedded systems. Sometimes it is also possible to use mixed approaches like in [9], where a software estimation methodology tries to approach each step in the analysis with the best methods currently known is presented. Our approach fits in the second category, thus this one will be described more in detail below. In [6] a program timing analyzer for control applications is ....

R. Ernst and W. Ye, "Embedded program timing analysis based on path clustering and architecture classification," in Proc. Int. Conf. Computer-Aided Design, pp. 598--604, Nov. 1997.

....the gap when such stretching does not affect the application timing constraints. From the above discussion, we can notice that even PSPM is not optimal. Since dynamic power management is needed to save more energy by taking advantage of tasks actual run time behavior (which varies significantly [7]) we explore dynamic power management schemes next. 5 Dynamic Power Management Dynamic slack is generated when tasks of the application execute less than their worst case execution time. Dynamic power management is applied in addition to static power management and used to reclaim dynamic ....

R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proc. of The International Conference on Computer-Aided Design, pages 598--604, San Jose, CA, Nov. 1997.

....line block segments [4] high level program constructs [6] super block segments or inter block relations as well. Besides, a mixture of different analysis blocks for static timing analysis is conceivable. This complies with the hierarchical flow graph clustering and treatment of ERNST et al. [1]. In general, static reasoning about worst case timing is an undecidable problem due to the facts, that the executed program trace depends on the initial program state and the applied input values. To make this problem tractable, the program path model PM must not contain unbounded loops, any ....

R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings of the ICCAD-97, pages 598--604, Nov. 1997.

....we assume that the processor supply voltage and speed are always adjusted together, by setting the maximum speed under certain supply voltage. Since tasks exhibit a large variation in actual execution time, and in many cases, only consume a small fraction of their worst case execution time [11], any unused time can be considered as slack and can be reused by the remaining tasks to run slower while still finishing before D [2, 20] In this case, power and energy consumption is reduced. To get maximal energy savings, we combine static power management and dynamic voltage speed ....

R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proc. of The International Conference on Computer-Aided Design, pages 598--604, San Jose, CA, Nov. 1997.

....to as S jit . In addition to static power management, we may reduce energy further by using both dynamic supply voltage and speed adjustment. Since tasks exhibit a large variation in actual execution time, and in many cases, only consume a small fraction of their worst case execution time [9], any unused time can be considered as slack and can be reused by the remaining tasks to run slower while still finishing before D [6] In this case, processor power and energy consumption is reduced. To get maximal energy savings, we combine static power management and dynamic voltage speed ....

R.Ernst and W.Ye. Embedded Program Timing Analysis based on Path Clustering and Architecture Classification. In Computer-Aided Design (ICCAD)97. pp. 58-604. San Jose, CA, November 1997.

....in these studies, while using exclusively worst case execution time (WCET) to guarantee the timeliness of the system, lack the ability to dynamically take advantage of unused computation time. In fact, real time applications usually exhibit a large variation in actual execution times; for example [5] reports that the ratio of the worst case execution time to the best case execution time can be as high as 10 in typical applications. Consequently, dynamically monitoring and reclaiming the unused computation time can be (and, as we show later in this paper, is in fact) a powerful approach to ....

R. Ernst and W. Ye. Embedded Program Timing Analysis based on Path Clustering and Architecture Classification. In Computer-Aided Design (ICCAD)'97. pp. 598-604.

....in the above studies, while using exclusively worst case execution time (WCET) to guarantee the timeliness of the system, lack the ability to dynamically take advantage of unused computation time. In fact, applications usually exhibit a large variation in actual execution times; for example, [9] reports that the ratio of the worst case execution time to the best case execution time can be as high as 10 in typical applications. Consequently, dynamically monitoring and reclaiming the unused computation can be (and, as we show below, is in fact) a powerful approach to obtain ....

....program, then C i = C i#(1) represents the worst case execution of the entire program P i . Although knowing the worst case execution scenario of a task is essential to guarantee that a task meets its deadline, usually a program, P i , executes for much less than its worst case estimate, C i [9]. This is because the input data and system architecture (e.g. the amount of cache in the system) determine not only the actual number of cycles the segment executes (typically less than C i ) but also determines the execution path of P i . If we denote by C avg i#( j) the average number of ....

R. Ernst and W. Ye. Embedded Program Timing Analysis based on Path Clustering and Architecture Classification. In Computer-Aided Design (ICCAD)'97. pp. 598-604.

....all tasks at maximum frequency. After that the task schedule is adjusted until no further reduction is possible without violating deadlines. The ratio between the actual execution time and the WCET can be quite low: an average of 0. 5 is reported for several hard real time applications studied in [22]. When the WCET is not an accurate estimation of the execution time, the assigned clock frequencies to meet deadlines tend to be too high (factor of 2 on average) Consequently, a task usually finishes early, and an idle periods occurs. If another task is eligible for execution, however, the idle ....

R. Ernst and W. Ye, "Embedded program timing analysis based on path clustering and architecture classification," in International Conference on Computer Aided Design, Nov. 1997, pp. 598--604.

....(e.g. bychanging the state of the cache. assembler loader Functional C code Object code executable Target translator Simulator Annotated C code ASM2C source annotator Figure 1: Simulation preparation ow. Mixed approaches can be used under some circumstances. For example, [8] tries to approacheach step in the analysis with the best currently known methods. 3. SOURCE BASED ESTIMATION The estimation ows discussed in this paper are shown in gure 1. In this section we focus on the ow depicted on the right, based on direct annotation of the C source. The key idea is ....

R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classication. In ##### #### ##### ############## ######, pages 598604, Nov. 1997.

....program execution time is modeled by: T prg = T 100 hit N miss;r # N cyc;r penalty N miss;w # N cyc;w penalty N miss;f # N cyc;f penalty (3) 3.3 Design Flow of our Framework The input is a C program (Fig. 1) of the application 5 . The upper branch comprises a behavior simulator [23] that is attached to our software energy and performance models (Eq. 2 and 3) The branch below contains the trace tool QPT and the Dinero III [19]cache simulator who feeds software, cache and main memory energy models with the numbers of total cache accesses, data cache hits, data cache misses ....

R. Ernst, W. Ye, Embedded program timing analysis based on path clustering and architectural classification, IEEE Proc. of Int. Conf. on CAD (ICCAD97), pp.598-604, 1997.

....system code. Colin and Puaut [8] have investigated parts of the code for the RTEMS operating system, and found no nested loops, unstructured code, or recursion. To the extent covered by their investigation, operating system code can be considered a well behaved special case. Ernst and Ye [17] reach some interesting conclusions regarding the actual program flow of some common signal processing algorithms. While the program source code contains lots of decisions and loops, the decisions are structured in such a way that there is only a single path through the program regardless of ....

R. Ernst and W. Ye. Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification. In International Conference on Computer-Aided Design (ICCAD '97), 1997.

.... benefits of separating the interfaces of components from their internal behavior computation, starting with the system specification stage through the system refinement stages, were presented in [2] Various techniques have been proposed for performance analysis of hardware [3, 4] and software [5, 6]. System level performance analysis techniques which consider the effects of communication can be broadly divided into the following categories: # Approaches based on simulation of the entire system using models of the components and their communication at different levels of abstraction [2, 7] ....

R. Ernst and W. Ye, "Embedded program timing analysis based on path clustering and architecture classification," in Proc. Int. Conf. Computer-Aided Design, pp. 598--604, Nov. 1997.

.... we have developed efficient techniques to identify program segments (PrS) with unique paths and exploit such segments to reduce analysis problem size and safely reduce timing intervals [11, 13] Large parts of typical embedded system programs have a single path that is independent of input data [14]. An example is given in the graph in figure 2, other examples may be an FFT or an FIR filter. The control flow of the loop is independent of input data. This path may wrap around many loops, conditional statements and even function calls that are used for source code structuring and compacting. A ....

....of cache line contents that could have been leading to a hit. If the data access address is composed by the base address, constants and variables resulting from a local access sequence in an SFP PrS. e.g. as for the array a in figure 2, this is referenced to as a Single Data Sequence (SDS) [14] which is quite common in embedded systems. Data cache behavior of SDS can be determined by local simulation of the program segment. 3.5 Program Segment Cache Evaluation Simulation for SFP PrS starts with the best case and worst case assumptions being first hit miss regarding the contents at the ....

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W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD '97), pages 598--604, San Jose, USA, 1997.

....bases on designer interaction for the determination of the longest path while abstract interpretation is used for the static prediction of cache and pipeline behavior. Abstract interpretation can also be used to reduce excessive designer interaction for loop bounding [10] In our approach based on [27], symbolic execution extends abstract interpretation for automatic path analysis with reduced designer interaction. The alternative of a statistical approach using branching probabilities is proposed by Gong and Gajski [8] 2.4 Local Execution Cost Models The execution time model in [16] is ....

....in program segments can be considered. This shall be called the sum of program segments model. This model shall be discussed in the sequel. 2.5 Basic Path Classification Many false paths can be identified by program properties such as variable dependencies alone. The analysis technique in [27] has been extended for that purpose. Program properties can be exploited to simplify path analysis for the determination of the program segment cost through basic block sequences. Large parts of typical embedded system programs have a single program path only. An FIR filter is a simple example and ....

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W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings of ICCAD '97, pages 598--604, San Jose, USA, 1997.

....only partially. The user has to add a modeling of the environment including timing constraints and processes modeling signal sources and sinks and operating system components. 2. 2 SYMTA The parameter extraction for the mapping to the SPI model is based on SYMTA (SYMbolic hybrid Timing Analysis) [4], a timing analysis tool that combines formal analysis and simulation. The input representation is a control and data flow graph (CDFG) that is currently derived from the C language but can be easily adapted to all imperative programming languages. Based on the CDFG and possible user annotations, ....

W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings International Conference on Computer-Aided Design (ICCAD '97), San Jose, USA, 1997.

....of cache and pipeline behavior. Abstract interpretation has also been used to reduce designer interaction for loop bounding [6] 2.2. Execution Cost The execution time model in [7] is established as a standard model for static approaches which is called the sum ofbasic blocks model in [13] for timing. It can be extended to power consumption [11] and data rates, abstracting the timing to the execution cost c of a program segment in general. Let a program consist of N basic blocks with x i execution count of basic block bb i and c i execution cost. Then, the sum of basic blocks model ....

....the sum of program segments model containing basic block sequences which is a major improvement compared to the state of the art. 2.3. Path Classification Program properties can be exploited to simplify path analysis for the determination of the execution cost through basic block sequences [13]. Large parts of typical embedded system programs have a single program path only. An FIR filter is a simple example and a Fast Fourier Transform is a more complex one. There is only one path executed for any input pattern, even though this path may wrap around many loops, conditional statements ....

[Article contains additional citation context not shown here]

W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings International Conference on Computer-Aided Design (ICCAD '97), pages 598--604, San Jose, USA, 1997.

....basic block cache tables to identify upper and lower bounds for the number of cache line replacements, hits and misses per basic block execution. Then, based on implicit or explicit program path analysis, upper and lower bounds on the total cache hits and misses are determined. In earlier papers [15, 14], we have demonstrated how to extend analysis elements from basic blocks to larger program segments thereby significantly improving both path analysis and architecture modeling precision. The approach is based on local program segment execution, i.e. cycle true simulation. These program segments ....

....of access addresses can be used by any tool suite. 3. Trace Based Cache Simulation A method that delivers tight bounds for the cache behavior of a single process on a given target architecture is proposed. Input data independent program segments covering several basic blocks are found [15, 14] and can be simulated with any trace based cache simulator. 3.1. From Basic Blocks to Program Segments For trace based cache analysis, executable program segments have to be isolated. The program path analysis model in [11] is established as a standard model for static approaches, while it ....

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W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings of ICCAD, pages 598--604, San Jose, 1997.

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R. Ernst and W. Ye, "Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification", Proc. Int. Conf. on CAD, 1997, pp. 598-604.

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R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proc. International Conference on ComputerAided Design (ICCAD '97), San Jose, USA, 1997.

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R. Ernst and W. Ye. Embedded Program Timing Analysis based on Path Clustering and Architecture Classification. In Computer-Aided Design (ICCAD'97), pages 598--604, 1997.

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R. Ernst and W. Ye, "Embedded program timing analysis based on path clustering and architecture classification," in Proc. Int. Conf. ComputerAided Design, Nov. 1997, pp. 598--604.

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R. Ernst and W. Ye. Embedded Program Timing Analysis based on Path Clustering and Architecture Classification. In Computer-Aided Design (ICCAD)'97. pp. 598-604.

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R. Ernst and W. Ye. Embedded Program Timing Analysis based on Path Clustering and Architecture Classification. In Computer-Aided Design (ICCAD)'97. pp. 598-604.

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R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proc. of The International Conference on Computer-Aided Design, pages 598--604, Nov. 1997.

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W. Ye and R. Ernst, "Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification, " Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1997, pp. 598-604.

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