Thacker, R. A. Implicit methods for timed circuit synthesis. Master's thesis, University of Utah, 1998. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Modular Synthesis And Verification Of Timed Circuits Using.. - Zheng (Correct)
....is based on an ordered binary decision diagram [23] It represents logic functions which express transition relations between states. OBDDs provide a canonical form for boolean functions which is substantially more compact, and very ecient algorithms have been developed for manipulating them. In [76], an implicit method using multiterminal BDDs was described. Because the symbolic representation captures some of the regularity in the state space of circuits, it can represent systems with an extremely large number of states [52] Although implicit methods are able to represent systems with ....
Thacker, R. A. Implicit methods for timed circuit synthesis. Master's thesis, University of Utah, 1998.
Stochastic Cycle Period Analysis in Timed Circuits - Mercer, Myers, Beerel (1999) (2 citations) (Correct)
....at a completed design. ATACS is a tool designed to take a specification of a control system annotated with timing assumptions [5] and output the resulting circuit. This tool uses many detailed algorithms to consider and verify the effects of the timing assumptions on a final implementation [6, 7]. Critical to any computer aided design (CAD) tool is the ability to analyze the relative merit of different design incarnations at different levels of the design process. ATACS provides many methods of verifying and synthesizing timed circuits, but previously not provide any type of performance ....
R. A. Thacker. Implicit methods for timed circuit synthesis. Master's thesis, University of Utah, 1998.
Stochastic Cycle Period Analysis In Timed Circuits - Mercer (1999) (2 citations) (Correct)
....arriving at a completed design. ATACS is a tool designed to take a speci cation of a control system annotated with timing assumptions [26] and output the resulting circuit. This tool uses many detailed algorithms to consider and verify the e ects of the timing assumptions on a nal implementation [3, 21]. Pivotal to any computer aided design (CAD) tool is the ability to analyze the relative merit of di erent design incarnations at di erent levels of the design process. ATACS provides many methods of verifying and synthesizing timed circuits but previously did not provide any type of performance ....
Thacker, R. A. Implicit methods for timed circuit synthesis. MS thesis, University of Utah, 1998.
Stochastic Cycle Period Analysis In Timed Circuits - Mercer (2000) (2 citations) (Correct)
....at a completed design. ATACS is a tool designed to take a specification of a control system annotated with timing assumptions [26] and output the resulting circuit. This tool uses many detailed algorithms to consider and verify the effects of the timing assumptions on a final implementation [3, 22]. Pivotal to any computer aided design (CAD) tool is the ability to analyze the relative merit of different design incarnations at different levels of the design process. ATACS provides many methods of verifying and synthesizing timed circuits, but previously did not provide any type of ....
Thacker, R. A. Implicit methods for timed circuit synthesis. Master's thesis, University of Utah, 1998.
Algorithms For Synthesis And Verification Of Timed Circuits And .. - Belluomini (1999) (3 citations) (Correct)
....regions generated, or reducing the size of the stack. To further reduce the amount of memory needed, implicit methods can be used to more efficiently represent the state space. This chapter describes a method for representing geometric regions using implicit methods, first presented by Thacker in [66, 65], which significantly increases the size of specification that can be analyzed. 7.1 Representing Geometric Regions Much of the data compiled during state space exploration consists of bit vectors. Therefore, Bryant s binary decision diagrams (BDDs) which are a highly efficient method for ....
Thacker, R. A. Implicit methods for timed circuit synthesis. Master's thesis, University of Utah, 1998.
Verification of Timed Systems Using POSETs - Belluomini, Myers (1998) (15 citations) (Correct)
....and we are interested in trying to combine them for further improvement. Finally, our algorithm currently represents the state space explicitly, and we are working on applying implicit techniques. Our preliminary results show that this can lead to a significant improvement in memory performance [25]. Acknowledgments We would like to thank Mark Greenstreet of the University of British Columbia, Brandon Bachman, Eric Mercer, and Robert Thacker of the University of Utah and Tom Rokicki of Hewlett Packard for their helpful comments. ....
R. A. Thacker. Implicit methods for timed circuit synthesis. Master's thesis, University of Utah, 1998.
Stochastic Cycle Period Analysis in Timed Circuits - Mercer (1999) (2 citations) (Correct)
....at a completed design. ATACS is a tool designed to take a specification of a control system annotated with timing assumptions [26] and output the resulting circuit. This tool uses many detailed algorithms to consider and verify the effects of the timing assumptions on a final implementation [3, 21]. Pivotal to any computer aided design (CAD) tool is the ability to analyze the relative merit of different design incarnations at different levels of the design process. ATACS provides many methods of verifying and synthesizing timed circuits but previously did not provide any type of ....
Thacker, R. A. Implicit methods for timed circuit synthesis. MS thesis, University of Utah, 1998.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC