B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge, "An Analytical Model for Designing Memory Hierarchies", IEEE Transactions on Computers, Vol. 45, No. 10, 1996, pp. 1180-1194.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....to outperform object caching. Khalid and Obaidat have recently proposed neural network based cache replacement algorithms [79, 62] for eliminating inactive cache lines and achieved 8.71 improvement over LRU. Jacob et al. give an analytical model for hardware related design of memory hierarchies [58]. Processor caches and hardware related optimizations are out of the scope of this research. 2.3 Caching and Adaptivity in Distributed File Systems (DFS) Distributed file systems that allow clients to cache file data and also allow sharing need to provide cache consistency; a coherent view of ....

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. ACM Transactions on Computer Systems, 45(10):1180--1194, 1996.

....[13] 22] 10] None of these approaches determine the best memory hierarchy organisation for a given application and they do not directly address the power cost. An analysis of memory hierarchy choices based on statistical information to reach a given throughput expectation has been discussed [9]. More recently, dynamic management of a scratch pad memory for temporal and spatial reuse has been addressed [11] In the hardware realization context, much less work has been performed, mainly oriented to memory allocation [17] 25] 1] 26] 4] The impact of the data reuse exploration step turns ....

B. Jacob, P. Chen, S. Silverman, and T. Mudge. An analytical model for designing memory hierarchies. IEEE Trans. on Computers, C-45(10):1180--1193, 1996.

....caches employ an exponential or power function model for the change in working set over time. These models have been extended to account for a range of line sizes[4, 5] Other models have been developed for direct mapped caches [6] instruction caches [7] 8] multi level memory hierarchies [9], and multiprocessor caches [10] The analytic cache model by Agarwal et al., referred to subsequently as the AHH model, estimates the miss rate of setassociative caches using a small set of trace parameters derived from the address trace [11] The AHH model has been validated by determining the ....

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge, "An Analytical Model for Designing Memory Hierarchies," IEEE Transactions on Computers, vol. 45, pp. 1180-94, 1996.

....those ones obtained by simulation. That happens because the over simplification of the models. The research activity on analytical modeling field is quite intensive and many computer systems (and architectures) are being modeled and evaluated using such methodology ( MAR 84] SAA 90] YAM 94] JAC 96] e [KAN 97] CAR 97] COU 91] GUN 98] ROB 94] SAH 96] SIL 92] In [YAM 94] the results obtained by an analytical model differs only by 4 of the ones obtained by conventional simulation showing that even simple models can produce good results. In this work, a tool called DSPNExpress ....

Jacob, B. L.; Chen, P. M.; Silverman, S. R.; Mudge, T. N.: An Analytical Model for Designing Memory Hierarchies IEEE Transactions on Computer, Vol. 45, No. 10, Oct/1996.

....execution and being restricted to a specific platform. A more general approach is that of analytical models, which, in addition to requiring short computation times, make more flexible the parametric study of the cache. Although many models extract input parameters from address traces [3] 4] [5] and combine them with cache definition parameters, more general purpose models have been developed taking as input the code to analyze [6] 7] 8] Nevertheless these models only consider dense algebra codes, with regular access patterns. There are very few works related to the analytic ....

B.L. Jacob, P.M. Chen, S.R. Silverman and T.N. Mudge, An Analytical Model for Designing Memory Hierarchies, IEEE Transactions on Computers 45 (1996) 1180-- 1194.

....through a simulator to determine hit rates or average memory access times. Occasionally in the past and more often now, researchers are taking a different approach and attempting to design not just a better cache, but better ways to design and analyze caches through new models or measures [1, 3, 5, 7, 8, 9, 12, 13, 14, 16]. This paper describes an analytical framework for cache design. There are four major components that form the framework, each of which is a contribution on its own. First, the TSpec notation is a more formal way for researchers to communicate with clarity about memory references generated by a ....

B. Jacob, P. Chen, S. Silverman, T. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10):1180-94, October 1996.

....the same size. 2.3 Workload characterization The workload characterization on SMPs is mainly based on the probabilities of references to different levels of the memory hierarchy. The probability is determined based on stack distance curves taken directly from an address stream [5] The work in [9] uses the same approach for evaluating the performance of memory hierarchies of uniprocessor systems. In general, the stack distance of datum A at one position of the address stream is the number of unique data items between this reference and the next reference to A. The distribution of stack ....

....of references within a given stack distance of x. This fits an LRU managed and fully associative cache hitting rate well if x is considered as the cache size. The probability density function, denoted p(x) describes the frequency of references at stack distance x. Similar to other related work [9,13,14], we model P (x) and p(x) in the form of P (x) 1 Gamma 1 (x=fi 1) ff Gamma1 ; and p(x) fi ff Gamma1 (ff Gamma 1) x fi) ff ; 1) where ff 1 and fi 1 are workload parameters to characterize locality of a program. The program locality improves with the decrease of fi or the ....

[Article contains additional citation context not shown here]

B. L. Jacob, P. M. Chen, S. R. Silverman, T. N. Mudge, An Analytical Model for Designing Memory Hierarchies, IEEE Trans. Computers, 45 (1996) 1180-1194.

....shared memory in the cluster. Our execution model of cluster computing is mainly based on the probabilities of references to different levels of the memory hierarchy in Figure 1. The probability is determined based on stack distance curves taken directly from an address stream [6] The work in [15] uses the same approach for evaluating the performance of memory hierarchies of uniprocessor systems. In general, the stack distance of datum A at one position of the address stream is the number of unique data items between this reference and the next reference to A. The distribution of stack ....

....of references within a given stack distance of x. This fits an LRU managed and fully associative cache hit rate well if x is considered as the cache size. The probability density function, denoted p(x) describes the frequency of references at stack distance x. Similar to other related work [15, 20, 22], we model P (x) in the form of P (x) 1 Gamma 1 (x=fi 1) ff Gamma1 ; 2.1) 5 thus p(x) in the form of p(x) fi ff Gamma1 (ff Gamma 1) x fi) ff ; 2.2) where ff 1 and fi 1 are workload parameters to characterize the locality of a program. The program locality improves with ....

[Article contains additional citation context not shown here]

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge, "An Analytical Model for Designing Memory Hierarchies", IEEE Transactions on Computers, Vol. 45, No. 10, 1996, pp. 1180-1194.

....(CICYT) of Spain under project TIC96 1125 C03 obviously limited to the study of the architectures where these devices exist, and it still gives little information on the cache behavior. On the other hand, there are analytical models that extract their input parameters from address traces [2] [10], which requires execution or simulation of the program each time any of its parameters changes, just as the two previous approaches. There are very few analytical models based directly on the code [8] 13] and most of them are oriented to direct mapped caches. Besides very little efforts have ....

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10):1180-- 1194, Oct. 1996.

.... both uni and multiprocessor systems, but the amount of data stall time tends to increase with the number of processors in a multiprocessor system [2] The data stall time is related to the miss rate in the data cache and a simple solution to reduce the miss rate is to increase the block size [1] [11]. However, increasing the block size tends to introduce other problems, such as cache pollution [7] 23] since the characteristics of spatial locality varies among different data. 3 Spatial Locality In this section, we start in Section 3.1 by establishing the critical parameters for techniques ....

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge, "An Analytical Model for Designing Memory Hierarchies," IEEE Transactions on Computers, Volume 45, Number 10, pp. 1180-1194, October 1996.

....[9] None of these approaches determine the best memory hierarchy organization for a given (set of) applications and only few address the power cost. Only an analysis of memory hierarchy choices based on statistical information to reach a given throughput expectation has been discussed recently [10]. In the hardware realization context, much less work has been performed, mainly oriented to memory allocation [11] 12] 13] This paper discusses how to decide on the optimal use of the memory in a systematic way. III. Memory Hierarchy Design This section defines the memory hierarchy design ....

B.Jacob, P.chen, S.Silverman, T.Mudge, "An analytical model for designing memory hierarchies", IEEE Trans. on Computers, Vol.C-45, No.10, pp.1180-1193, Oct. 1996.

....improvements to the cache configuration or the code structure. A This work was supported by the Ministry of Education and Science (CICYT) of Spain under project TIC96 1125 C03 better approach is that of analytical models that extract some of their input parameters from address traces [1] [6], although they still need the generation of the trace each time the program is changed. Finally, there are a few analytical models based directly on the code [9] 4] and most of them are oriented to direct mapped caches. The last one has been implemented in an optimizing environment and later ....

Jacob, B.L., Chen, P.M., Silverman, S.R., Mudge, T.N.: An analytical model for designing memory hierarchies. IEEE Transactions on Computers. 45(10) (1996) 1180--1194

....its performance prediction. Cache miss rates can be derived by trace driven simulations [10] which although being very accurate lack flexibility and consume many computing resources. Another approach is that of analytical models that extract their input parameters from address traces [2] [6], thus requiring the This work was supported by the Comision Interministerial de Ciencia y Tecnolog ia (CICYT) under project TIC96 1125, Xunta de Galicia under Project XUGA20605B96 program execution or simulation each time any of its parameters changes. The same problem arises when we use the ....

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10):1180-- 1194, Oct 1996.

....kernel such as sparse matrix vector product using real matrices from the HarwellBoeing [4] and NEP [1] collections. Trace driven simulations are a common method for the estimation of code performance. Another usual approach is the use of models that derive their input parameters from traces [3] [7], 9] Probabilistic models reduce estimation times and provide more flexibility for the parametric study of the cache. There are few previous works on this type of modeling of cache per This work was supported by the Comision Interministerial de Ciencia y Tecnolog ia (CICYT) under project ....

B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10):1180-- 1194, Oct 1996.

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B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge, "An Analytical Model for Designing Memory Hierarchies", IEEE Transactions on Computers, Vol. 45, No. 10, 1996, pp. 1180-1194.

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Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, and Trevor N. Mudge. "An Analytical Model for Designing Memory Hierarchies". IEEE Trans. Comput., 45(10):1180--1194, 1996.

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B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10):1180-- 1194, Oct 1996.

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B.L. Jacob, "An analytical model for designing memory hierarchies", IEEE Transaction on Computers, volume 45, pp. 83-105, 1996.

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B.Jacob, P.chen, S.Silverman, and T.Mudge, "An analytical model for designing memory hierarchies," IEEE Trans. on Computers, vol. C-45, no. 10, pp. 1180-- 1193, Oct. 1996.

No context found.

B.L. Jacob, P.M. Chen, S.R. Silverman, and T.N. Mudge. An Analytical Model for Designing Memory Hierarchies. IEEE Transactions on Computers, 45(10):1180--1194, October 1996.

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B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An analytical model for designing memory hierarchies. ACM Transactions on Computer Systems, 45(10):1180--1194, 1996.

No context found.

B.Jacob, P.Chen, S.Silverman, and T.Mudge. An analytical model for designing memory hierarchies. IEEE Trans. on Computers, C-45(10):1180--1193, 1996.

No context found.

Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, and Trevor N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10):1180--1194, 1996.

No context found.

Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, and Trevor N. Mudge. An analytical model for designing memory hierarchies. IEEE Transactions on Computers, 45(10), October 1996.

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JAC96 B. Jacob, P. Chen, S. Silverman, T. Mudge. "An Analytical Model for Designing Memory Hierarchies," IEEE Transactions on Computers, vol. 45, no 10, October, 1996.

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