Wm. A. Wulf. The WM computer architecture. Computer ArchitectureNews, 16(, March 1988.  Home/Search Document Not in Database Summary Related Articles Check |
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Hyperscalar Processor Architecture - Murakami, Miyajima, Saitoh.. (Correct)
....tions are allowed to access vector registers for computation, a more flexible loop transformation technique than vectorization, i.e. software pipelining can be used. This is a disadvantage of vector processors against scalar or VLIW processors with a large register file, such as WM computer [11], Cydra5 [10] 3 Hyperscalar Processor Architecture Hyperscalar processor architecture tries to include the above mentioned advantages and exclude the disadvantages of superscalar, VLIW, and vector processor architectures. Memo IR 0 Data Cache Instruction Cache FUo FU 1 FU 2 (L S) ....
Wulf, W. A., "The WM Computer Architecture," ACM $IGARCH Com- put. Architect. News, vol.16, no.1, pp.70-84, Mar.1988. 23
Architectural Considerations in Silf-Timed Processor Design - Richardson (1996) (Correct)
....two or more independent instructions in parallel. Superscalar implementations provide dynamically scheduled instruction issue, often combined with out of order completion. Another effective approach lies in decoupling the memory access portion of an instruction stream from the execution portion [19,45]. The two operations are scheduled statically but are allowed to move in and out of phase dynamically. In this manner, peaks and valleys in each may be smoothed for an overall performance gain. It has been shown [15] that the decoupled approach can provide a limited version of register renaming, ....
....general purpose registers, but r0 and r1 have special meaning. Register r0 may be used as the destination of an instruction but will always contain zero. Register r1 is not really a register at all but provides read access to the R1 Queue, a data pipeline similar to that used in the WM machine [45]. Specifying r1 as the destination of an instruction inserts the result into the pipeline. Each use of r1 as a source for an instruction retrieves one word from the R1 Queue. For example, the instruction add r2,r1,r1 would fetch two words from the R1 Queue, add them together, and place the sum in ....
[Article contains additional citation context not shown here]
W. A. Wulf, "The WM computer architecture," Computer Architecture News, vol. 16, March 1988.
The Multiscalar Architecture - Franklin (1993) (34 citations) (Correct)
....is that the superscalar hardware has no access to the higher level control flow of the program; all the control flow information that it has is what is obtained in a step by step manner by the decoding of instructions. There have been several proposals for superscalar machines in the 1980s [4, 33, 87, 101, 119, 120, 134, 135, 155, 156, 164]; notable ones include the IBM Cheetah, America and RIOS projects which culminated in the IBM RS 6000 [66, 111] decoupled architectures, which resulted in the Astronautics ZS 1 [137, 139] and HPS [73, 116] Advantages of the superscalar approach include object code compatibility and the ability ....
W. A. Wulf, "The WM Computer Architecture," Computer Architecture News, vol. 16, March 1988.
Hyperscalar Processor Architecture - Murakami, Miyajima, Saitoh.. (Correct)
....are allowed to access vector registers for computation, a more flexible loop transformation technique than vectorization, i.e. software pipelining can be used. This is a disadvantage of vector processors against scalar or VLIW processors with a large register file, such as WM computer [11], Cydra5 [10] 3 Hyperscalar Processor Architecture Hyperscalar processor architecture tries to include the above mentioned advantages and exclude the disadvantages of superscalar, VLIW, and vector processor architectures. Register File IR (L S) IR IR IR 0 1 2 f 1 FU FU FU FU 0 1 f 1 Decoder ....
Wulf, W. A., "The WM Computer Architecture," ACM SIGARCH Comput. Architect. News, vol.16, no.1, pp.70--84, Mar.1988.
Fred: An Architecture for a Self-Timed Decoupled Computer - Richardson, Brunvand (1995) (4 citations) (Correct)
No context found.
Wm. A. Wulf. The WM computer architecture. Computer ArchitectureNews, 16(, March 1988.
Limits on Multiple Instruction Issue - Smith, Johnson, Horowitz (1989) (78 citations) (Correct)
No context found.
W.A. Wulf, "The WM Computer Architecture". Architecture News (January 1988), pp. 70-84. 15
Evaluation of the WM Architecture - Wulf (1992) (30 citations) (Correct)
No context found.
Wulf, Wm. A., "The WM Computer Architecture", in Computer Architecture News, v16, n1, March 1988.
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