M. Boo, F. Arguello, J. D. Bruguera, R. Doallo, and E. L. Zapata. High-performance VLSI architecture for the Viterbi algorithm. IEEE Trans. Communications, 45(2):168--176, Feb. 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....fall within the region between the two dashed lines. While small state VDs can have throughput over 1 Gbps, throughput decreases with the increase in the number of states. Consequently, the design of high throughput large state VDs, though crucial for applications such as satellite communications [2], has remained largely unexplored. 2 4 8 16 32 64 128 256 512 2 1 Number of States Throughput (Mbps) 0.57W 0.35W 0.66W 0.75W 2W 6mW 3W 1.8W 0.01W 0.24mW 7.65mW 0.66W 0.45W Our Design Figure 1: Performance of various VDs. The main challenge in implementing ....

....adjacent trellis columns, pipelining cannot be used in parallel architectures. Interleaving requires changes in communication protocols and is inconvenient to apply [14] Intermediate solutions, where each ACS processor is shared by more than one trellis state, are promising for large state VDs [2, 20]. Many such architectures have been proposed, including systolic arrays [5] and 4 level cluster networks [11] These approaches tend to focus on scalability, overlooking power and performance optimization of the decoder. No operation scheduling has been used to reduce global buses. In [12] ....

M. Boo, F. Arguello, J. D. Bruguera, R. Doallo, and E. L. Zapata. High-performance VLSI architecture for the Viterbi algorithm. IEEE Trans. Communications, 45(2):168--176, Feb. 1997.

....that permits representing in a simple way the data flow between states of the trellis as well as its mapping onto a processor column. Mathematical models of this type have been developed for data flows associated with the FFT [13, 14] tridiagonal systems [15] and free forward convolutional codes [16]. However, these methodologies can only be applied to convolutional encoders with no feedback, and consequently, their extension to encoders with feedback is important. The use of a system with feedback implies the study of new data flows, and, in particular, each interconnection has different ....

....onto an ACS array of arbitrary size. 2 2 MAPPING OF TRELLISES OF ENCODERS WITHOUT FEEDBACK: PREVIOUS WORK In this section we present the mathematical model for the projection of free forward convolutional codes with no feedback onto area efficient architectures that has been recently developed [16] and which we will use as a base for the projection of encoders with feedback. A free forward encoder consists of a shift register with n 1 stages and k binary function generators. We denote as state the content of the n most significant bits of the shift register and N as the number of states ....

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M. B'oo, F. Arguello, J.D. Bruguera, R. Doallo, E.L. Zapata, High-Performance VLSI Architecture for the Viterbi Algorithm, To be published on IEEE Trans. on Communications. 18 CAPTION FOR TABLES AND FIGURES

....trellis diagram Most implementations for applications requiring high speed processing, employ a state parallel approach where one ACS is devoted to each state of the trellis. However, this approach is very expensive when the number of states is high. Alternatively, area efficient architectures [3] [4] where each ACS processes several states of the trellis in different cycles, can be used. In this kind of architectures the number of ACSs can be preset according to the speed and area requirements. In this paper, we present the implementation in an application specific integrated circuit of ....

....PM updating according equation (1) and c) Path storage and output sequence selection. The BM is computed as the Hamming distance from the values received from a noisy channel to the output produced in a noiseless channel. The architecture implemented is based on the mapping methology described in [3], where the global data flow of the Viterbi algorithm is described by means of three operators, concatenation, decimation and partial perfect unshuffle, which present an inmediate hardware projection. To this end, each state is represented by means of a three dimensional index [x; y; z] x u ; ....

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M. Boo, F. Arguello, J.D. Bruguera, R. Doallo and E.L. Zapata. High-- Performance VLSI Architecture for the Viterbi Algorithm. IEEE Trans. Communications (to appear).

....to obtain all the stages of the 1 step trellis. The M step ACS unit has N ACSs each one with SM pipelining stages. The 1 step ACS unit has P ACSs with S 1 pipelining stages, where P N . The number P of ACSs of the 1 step ACS unit can be chosen by the designer as a function of the area constraints [5, 6]. That is, there are two ways of reducing the area requirements: reducing the pipelining stages or reducing the number of ACSs of the 1 step ACS unit. An extended study of the adequate P and M values is presented later. Let s start with the simplest case in which P=N and SM=S 1 =S, that is, the ....

....ACS unit, S 1 , and to an arbitrary number of ACSs in the 1 step ACS unit. The condition M log 2 (N ) implies that the associated trellis is fully connected, that is, every transition between states is possible. The number of possible previous states is employed in the methodology presented in [5, 6] as the minimum number of ACSs. This way, the states with the same possible previous states are processed in the same group of ACSs and the routing and timing is simplified. Following this methodology, the minimum number of ACSs in the M step ACS unit is N, that is, the number of states of the ....

M. B'oo, F. Arguello, J.D. Bruguera, R. Doallo, E.L. Zapata, High-Performance VLSI Architecture for the Viterbi Algorithm, Submitted.

....5 0 2 3 6 7 6 7 FIFO 2 3 5 6 7 3 2 1 0 1 0 PS Figure 7. Example of pipelined area efficient system to each state, and the selection of the final paths are made afterwards. 4. PIPELINED AREA EFFICIENT SOLUTIONS The third solution is based on the utilization of a pipelined area efficient solution [4]. The area efficient solutions enable us to reduce the area requirements and, on the other hand, to employ pipelined ACS units in an efficient way. The objetive of the area efficient methodologies is the computation of an N state trellis on a system of P ACSs (P N ) To achieve this, scheduling ....

....on the other hand, to employ pipelined ACS units in an efficient way. The objetive of the area efficient methodologies is the computation of an N state trellis on a system of P ACSs (P N ) To achieve this, scheduling methodologies and reordering hardware are necessary. The solution presented in [4] is based on the utilization of P 2 FIFO queues of (N P) 2 cells for the data reorganization. Each pair of ACSs introduces the computed data into two cells of a FIFO queue and, after the writing operation, the right shift of the FIFO queues must be carried out, freeing the input cells for the ....

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M. B'oo, F. Arguello, J.D. Bruguera, R. Doallo, and E.L. Zapata. High-Performance VLSI Architecture for the Viterbi Algorithm. In IEEE Trans. on Communications, volume 45, pages 168--176, Feb 1997.

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