V. Kathail, M. Schlansker, and B. Rau, "HPL PlayDoh Architecture Specification: Version 1.0," Technical Report HPL-93-80, HewlettPackard Laboratories, Feb. 1993. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
First 50 documents Next 50
Program Decision Logic Optimization Using Predication And.. - Hwu, August, Sias (2001) (Correct)
....operations, and, on virtually every instruction, a guard predicate operand. An instruction whose guard predicate is true executes; all others are nullified. Instances of predication presented in this paper are in the IMPACT EPIC style [4] which subsumes the predication models of both HPL PD [5] and Intel s Itanium family [6] IMPACT EPIC predicate define instructions generate two Boolean values using a comparison of two source operands and a guard predicate. A predicate define instruction has the form As will soon be discussed, some types of predicate defines are exceptions to this ....
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL PlayDoh architecture specification: Version 1.0," Hewlett-Packard Laboratories, Palo Alto, CA, Tech. Rep. HPL-93-80, Feb. 1994.
Architecture Exploration of Parameterizable EPIC SOC.. - Ashok Halambi Radu (2000) (Correct)
....multicycling units, and with varied latency configurations. Our experiments uncovered several non intuitive architecture design points, giving the system level designer further flexibility in exploration of programmable SOC architectures. 2 HPL PD EPIC Architecture We use the HPL PlayDoh (HPL PD)[4] a parametric EPIC load store architecture with both VLIW and Superscalar features as the platform for investigating the coupling of processor architecture and compiler technology. For EPIC style architectures, Register File (RF) ports are a critical resource, motivating the need for ....
V. Kathail, M. Schlansker, and B. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, HP Labs, 1994.
Phi-Predication for Light-Weight If-Conversion - Chuang, Calder, Ferrante (2003) (Correct)
....Conditional Writer predicated ISAs guard the writing of an instruction s register definition by a predicate register. If the predicate is true, the destination register gets assigned a new value, otherwise it retains the old value. The IA64 and PlayDoh predicated ISA falls under this category [10, 12], as does the conditional move (CMOV) operations like the Alpha ISA [22] In comparison to these, a select predicated ISA always writes the predicated definition by selecting from different input operands or constants. The Multiflow ISA provided a SELECT operation that used a general purpose ....
....optimize away extra CMOV s. While their examples show efficient code generation, the compile time cost maybe large. 2.3 PlayDoh and IA64 After Cydra 5 a series of architectures were created supporting heavy weight conditional writer predication. HP labs developed PlayDoh as described in [12, 18] as a testbed for new VLIW techniques. Subsequently HP and Intel collaborated to implement an evolved VLIW architecture called IA64 [10, 19] It features a heavy weight conditional writer predication model for an in order VLIW architecture. Virtually all non system instructions can be predicated. ....
V. Kathail, M. S. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, HP Labs, Feb 1994.
Fast Design Space Exploration through Validity and.. - Abraham, Rau, Schreiber (2000) (10 citations) Self-citation (Rau) (Correct)
No context found.
V. Kathail, M.S. Schlansker, and B.R. Rau, "HPL PlayDoh Architecture Specification: Version 1.1," Technical Report HPL-93-80 (R.1), Hewlett-Packard Laboratories, Feb. 2000.
ShiftQ: A bufferred interconnect for custom loop accelerators - Aditya, Schlansker (2001) (1 citation) Self-citation (Schlansker) (Correct)
....loop iterations. Software pipelining is traditionally used as a loop acceleration technique in conjunction with programmable VLIW processors that use multiported register files to store operands from the time that they are first computed until their final use. The use of rotating register files [4] allows register lifetimes to persist for multiple loop iterations without being overwritten in subsequent iterations. Multiple copies of the same virtual register (VR) corresponding to multiple loop iterations executing simultaneously are collectively referenced as expanded virtual registers ....
....a width threshold of 20 , i.e. a new ShiftQ class is generated if the width of an EVR differs from an existing class by more than 20 . Finally, another space saving heuristic used traditionally in unified rotating register files is to allocate EVRs in a modulo wrapped manner (closed loop model) [4] therebysaving Unit Mux se se se se C 0 . C II 1 . pse . PrefixQ ShiftQ 10 Figure 9: The ShiftQ PrefixQ schema. some space as opposed to allocating them in a sliding window (open loop model) This takes advantage of the fact that all registers in the unified file effectively ....
V. Kathail, M. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, Hewlett-Packard Laboratories, Feb. 1994.
Meld Scheduling: A Technique for Relaxing Scheduling.. - Abraham, Kathail, Deitrich (1998) (1 citation) Self-citation (Kathail) (Correct)
....section summarizes the results of this work. 2 Architecture models As we have discussed earlier, meld scheduling can improve the performance of both VLIW and superscalar processors. For most of this paper, we use a family of non interlocked VLIW machines based on the HPL PlayDoh architecture [8]. However, in Sections 3.10 and 4.3, we extend and evaluate meld scheduling algorithms on in order interlocked superscalar processors. Each machine has a set of integer, floating point, memory and branch units and is capable of issuing an instruction containing several operations in each cycle. ....
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL PlayDoh architecture specification: Version 1.0," HewlettPackard Laboratories, Palo Alto CA, Technical Report HPL-93-80, 1993.
Bitwidth Cognizant Architecture Synthesis of.. - Mahlke.. (2001) (3 citations) Self-citation (Schlansker) (Correct)
....accelerator datapath schema used by PICO. FUs include adders, multipliers, multiply adders, ALUs, etc. Ports to memories are treated as FUs as well. The physical memories and memory interfaces are not shown. There is also a special branch FU that controls the software pipeline loop execution [9]. Each FU computes result operands that must be stored in registers until they are no longer needed. Our approach for deploying registers is too complex to fully describe within this paper but a brief overview is presented here. A separate set of registers is dedicated to storing results that are ....
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL PlayDoh architecture specification: Version 1.0," Tech. Rep. HPL-93-80, Hewlett-Packard Laboratories, Palo Alto, CA 94304, Feb. 1994.
Height Reduction of Control Recurrences for ILP Processors - Michael Schlansker Vinod (1994) (22 citations) Self-citation (Kathail Schlansker) (Correct)
....dependences, are amenable to height reduction techniques such as symmetric and blocked back substitution [7] Predicate expressions as originally derived from programs may be too sequential in their construction. A set of properly defined machine operations, e.g. as in the PlayDoh architecture [21], can be used to parallelize the computation of these predicate expressions. This paper uses predicated execution to describe control height reduction. Similar control height reduction techniques can also be used to parallelize programs for architectures with no support for predicated execution. ....
....is that the architecture provides no support to schedule a load before potentially aliasing stores that precede the load in the original program. If the target architecture permits speculative stores or if the architecture provides data speculative loads (e.g. as in the PlayDoh architecture [21]) then the technique described in this paper can be applied to loops without the separable store property; however, that is beyond the scope of this paper. Given a separable loop, the state vector X can be decomposed into two parts S and T such that the following holds. The state vector S ....
[Article contains additional citation context not shown here]
V. Kathail, M. S. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, Hewlett-Packard Laboratories, Palo Alto CA, 1993.
Automatic architectural synthesis of VLIW and EPIC processors - Aditya, Rau, Kathail (19 citations) Self-citation (Kathail Rau) (Correct)
.... VLIW style of architecture, the space of processors that we are interested in exploring includes features such as predication, control and data speculation, rotating registers, and explicit source and destination specifiers for load and store operations at various levels of the memory hierarchy [9]. Processors with these features have the ability to exploit high degrees of compiler specified ILP both in numerically intensive applications as well as in applications that are intensive in branches and pointer based memory references. The architecture synthesis system that we describe in this ....
....to retarget the compiler. The system outputs a RTL level, structural VHDL description of the processor and estimates the chip area consumed by it. The third sub system consists of Elcor, our retargetable compiler for VLIW processors whose operation repertoire is a subset of the HPL PD repertoire [9], and a retargetable assembler. Both are automatically retargeted by supplying the machine description database. Elcor s responsibility is to generate the best possible code for the application on the processor designed by the VLIW architecture synthesis subsystem, and to evaluate its performance ....
V. Kathail, M. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL93 -80, Hewlett-Packard Laboratories, Feb. 1994.
Partitioning Variables across Register Windows to.. - Ravindran.. (2005) (Correct)
No context found.
V. Kathail, M. Schlansker, and B. Rau, "HPL PlayDoh Architecture Specification: Version 1.0," Technical Report HPL-93-80, HewlettPackard Laboratories, Feb. 1993.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION.. - In Architecture.. (Correct)
No context found.
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL Playdoh architecture specification: Version 1.0," Hewlett-Packard Labs., Santa Rosa, CA, Tech. Rep. HPL-93-80, 1994.
A Compiler Perspective on Architectural Evolutions - Nicholas Mitchell Larry (1997) (2 citations) (Correct)
No context found.
Vinod Kathail, Michael Schlansker, and B. Ramakrinsha Rau, "HPL PlayDoh architecture specification: Version 1.0," Tech. Rep. HPL-93-80, Hewlett-Packard Company, Computer Systems Laboratory, Feb. 1994.
Automatically Generating Custom Instruction Set Extensions - Clark, Tang, Mahlke (2002) (2 citations) (Correct)
No context found.
V. Kathail, M. Schlansker, and B. Rau, "HPL PlayDoh architecture specification: Version 1.0," Tech. Rep. HPL-93-80, Hewlett-Packard Laboratories, Feb. 1993.
RC23261 (96754) March 19, 1999 Electrical Engineering .. - Decoupled.. (Correct)
No context found.
V. Kathail, M. Schlansker, B. R. Rau, "HPL PlayDoh Architecture Specification: Version 1.0," HPL-93-80, February 1994.
Techniques for Accurate Performance Evaluation in.. - Hadjiyiannis, Devadas (2003) (2 citations) (Correct)
No context found.
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL Playdoh architecture specification: Version 1.0," Hewlett-Packard Labs., Santa Rosa, CA, Tech. Rep. HPL-93-80, 1994.
Adaptive Explicitly Parallel Instruction Computing - Surendranath Talla Of (2000) (4 citations) (Correct)
No context found.
V. Kathail, M. Schlansker, and B. Rau. HPL PlayDoh Architecture Specification Version. Technical report HPL-93-80, Hewlett-Packard Laboratories, Technical Publications Department, 1501 Page Mill Road, Palo Alto, CA 94304., 1994.
Compiler-Architecture Exploration using - Reservation Tables Generation (Correct)
No context found.
V. Kathail, M. Schlansker, and B. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, HP Labs, 1994.
A Co-simulation Study of Adaptive EPIC Computing - Valentin Stefan Gheorghita (Correct)
No context found.
V. Kathail, M. Schlansker, and B. Rau. HPL PlayDoh Architecture Specification Version. Technical Report HPL-9380, Hewlett Packard Laboratories, Technical Publication Department, 1501 Page Mill Road, Palo Alto, CA 94304, 1994.
Efficient Backtracking Instruction Schedulers - Abraham (2000) (Correct)
No context found.
V. Kathail, M.S. Schlansker, and B.R. Rau, "HPL PlayDoh Architecture Specification: Version 1.1," Technical Report HPL-93-80 (R.1), Hewlett-Packard Laboratories, Feb. 2000.
Compiler and Hardware Predicated Dependency Analysis and Scheduling - Carter (2002) (Correct)
No context found.
V. Kathail, M. S. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, HP Labs, Feb 1994.
Predicate-Aware Scheduling: A Technique for.. - Smelyanskiy.. (2003) (Correct)
No context found.
V. Kathail, M. Schlansker, and B. R. Rau. HPL PlayDoh Architecture Specifications: Version 1.0. HP Laboratories Technical Report HPL-93-80, 1994.
Automatically Generating Custom Instruction Set Extensions - Clark, Tang, Mahlke (2002) (2 citations) (Correct)
No context found.
V. Kathail, M. Schlansker, and B. Rau, "HPL PlayDoh architecture specification: Version 1.0," Tech. Rep. HPL-93-80, Hewlett-Packard Laboratories, Feb. 1993.
Optimizing Software Data Prefetches with Rotating Registers - Gautam Doshi Mission (2 citations) (Correct)
No context found.
V. Kathail, M.S. Schlansker, B.R. Rau, "HPL PlayDoh Architecture Specification: Version 1.0", HP Labs Technical Report, HPL-93-80, March 1994.
Turning Predicate Information to Advantage to Improve Compiler.. - Simon (2002) (Correct)
No context found.
V. Kathail, M. S. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, HP Labs, Feb 1994.
Master/slave Speculative Parallelization And Approximate Code - Zilles (2002) (1 citation) (Correct)
No context found.
V. Kathail, Micheal Schlansker, and Bob R. Rau. HPL PlayDoh Architecture Specification: Version 1.0. Technical Report HPL-93-80, HP Laboratories, February 1994.
First 50 documents Next 50
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC