Ulrich, E. 1983. A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Processor Self-Scheduling In Parallel Discrete Event Simulation - Konas, Yew (1995) (Correct)
....in a traditional event driven simulation. Previous work in the simulation area has shown that the most efficient data structure for event scheduling in simulations of detailed logic networks of large and active digital systems is the time wheel (Razdan, Bischoff, and Ulrich 1990, Ulrich 1980, Ulrich 1983). The time wheel actually consists of two data structures: a collection of linked lists containing scheduled future events (potential future activity in the simulated system) and a small hash table that maps the simulated time of an event occurrence to one of the linked lists. Analysis of this ....
Ulrich, E. 1983. A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression.
Parallel Simulations of Multiprocessors - Konas, Yew (1994) (Correct)
....time; a parallel simulation method has to find and expose the parallelism for efficient parallel execution. In contrast, architectural simulations are inherently synchronous; the activity during the simulation follows the changes of the clock signal(s) a behavior known as the clock effect [32, 39, 40]) Furthermore, such simulations contain significant amounts of inherent parallelism [36] Hence, the main problem in architectural parallel This work was supported in part by the National Science Foundation under Grant Nos. MIP 89 20891 and MIP 93 07910, NASA NCC 2 559, and a donation from ....
E. Ulrich. A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression. In Proceedings of 20th Design Automation Conference, pages 709--712, 1983.
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