A. Wahba and D. Borrione, \A method for automatic design error location and correction in combinational logic circuits", in J. of Electronic Testing: Theory and Applications, 1996, pp. 113-127.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....they were not precise in locating the error and used a fairly large number of test patterns to locate the error. Huang et al. 14] presented techniques for diagnosis for both sequential and combinational circuits by extensive enumeration and simulation. In some error model based approaches such as [15, 16], after the diagnosis is completed, the error is matched with an error type in the model and the implementation is recti ed accordingly. A general model for both fault and error diagnosis was proposed by Boppana et al. 17] and has been used to e ectively diagnose single errors in combinational ....

A. Wahba and D. Borrione, \A method for automatic design error location and correction in combinational logic circuits", in J. of Electronic Testing: Theory and Applications, 1996, pp. 113-127.

....the concepts and approach of our diagnostic and correction system. The results are given in Section 5, and our conclusions are presented in Section 6. 2 Prior Work Most combinational error diagnosis and correction approaches can be classified into two categories: 1) simulation based approaches [10, 14, 15, 20, 21, 22, 25, 26, 30], and (2) symbolic approaches [1, 9, 16, 17, 18] The simulation based approaches first derive a number of erroneous vectors. By simulating each erroneous vector, the potential error region can be trimmed down gradually. The conditions for eliminating those signals that cannot be an error source ....

A. M. Wahba and D. Borrione, "A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits," Journal of Electronic Testing: Theory and Applications, Vol. 8, No. 2, pp. 113-27, Apr. 1996.

....as to assist the subsequent error correction process. Due to the difficulty of diagnosing sequential circuits, most previous approaches have focused on combinational circuits. Most combinational error diagnosis approaches can be classified into two categories: 1) simulation based approaches [17,18,10,9,14,15,21], and (2) symbolic approaches [13,11,5,12] The simulation based approaches first derive a number of input vectors that can differentiate the implementation and the specification. These binary or 3 valued input vectors are called erroneous vectors hereafter. By simulating each erroneous ....

....The approach proposed in [6] is not very general in the sense that it only focuses on small feedbackfree circuits, or finite state machines that have one to one state correspondence with their specifications. Another approach, extending a combinational backward error propagation heuristic [21] to the iterative array model, was proposed in [20] In this approach, a restricted error hypothesis (containing three types of wrong gate errors) is used. It has two major limitations. First, it relies on a restricted error hypothesis, and thus, it may fail when the design error is not modeled in ....

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A. M. Wahba and D. Borrione, "A method for automatic design error location and correction in combinational logic circuits", Journal of Electronic Testing: Theory and Applications, vol.8, no.2, pp. 113-27, April 1996.

....problem. These approaches can be divided into two categories with respect to the underlying technique used for error location and error correction: those based on Boolean function manipulation (symbolic) techniques [8, 9, 10, 11, 16, 17, 18, 24, 27, 32] and those based on test vector simulation [13, 14, 15, 21, 22, 25, 26, 28, 29, 33, 34]. Techniques based on Boolean function manipulation have the advantage that they can return valid corrections, if such corrections exist in the design error model they use. They also have good error resolution and they are computationally e#cient for single errors. Nevertheless, their performance ....

....outline the steps of our DEDC methodology. For diagnosis, the method performs an implicit enumeration of error lines in an e#ort to avoid the exponential explosion of the error space (Eq. 1) and remain computationally e#cient. In detail, unlike most previous test vector simulation based approaches [13, 14, 15, 22, 25, 26, 28, 33, 34], it does not attempt to explicitly compute the complete error space and eliminate areas that cannot contain an error(s) Instead, it samples and searches a small area of the error space for error candidates. At the same time, correction uses an extension of the design error model of Abadir et al. ....

A. M. Wahba and D. Borrione, "A method for automatic design error location and correction in combinational logic circuits," in Journal of Electronic Testing, Theory, and Applications, vol. 8, no. 2, pp. 113-127, April 1996.

....to not only detect an error, but also to diagnose it, i.e. nowadays VLSI CAD tools should support features for error detection and correction. Diagnostic algorithms presented for Boolean networks so far work mainly on the gate level and thus the result is fixed to one specific design (see e.g. [12]) These approaches have the drawback that for each implementation of the function the error diagnosis has to be performed again, e.g. after resynthesis. In this paper we consider Sequential MVLNs (SMVLN) i.e. MVLNs with memory elements, on a higher level of abstraction. We model a SMVLN as a ....

A. Wahba and D. Borrione. A method for automatic design error location and correction in combinational logic circuits. Jour. of Electronic Testing: Theory and Applications, 8:113--127, 1996.

....this also reduces the production costs. For this, nowadays CAD tools should also support features for error diagnosis, i.e. error detection and correction. Diagnostic algorithms presented so far work only on the gate level and thus the result is fixed to one specific design (see e.g. [9]) These approaches have the drawback that for each implementation of the function the error diagnosis has to be performed again, e.g. after resynthesis. In this paper we consider SSCs on a higher level of abstraction, i.e. we consider a SCC as a Finite State Machine (FSM) and model the behavior ....

A. Wahba and D. Borrione. A method for automatic design error location and correction in combinational logic circuits. Jour. of Electronic Testing: Theory and Applications, 8:113--127, 1996.

....6) of the tests and the test generation time in seconds (column 11) are presented in Table 4. The goals of the experiments were twofold: to compare the efficiency (the speed of fault localization) of the new diagnostic approach (diagnostic preanalysis) in comparison with previous results [4]; to evaluate the design error diagnostic properties of test patterns generated by traditional gate level ATPGs for only stuck at fault detecting purposes. Experiments were carried out on the computer platform Sun SparcServer 20 (2 x Ultra Sparc II micro processors, 75MHz) with Solaris 2.5.1 ....

A.M. Wahba, D. Borrione. A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits. J. of Electronic Testing: Theory and Applications 8, 1996, pp. 113-127.

....hundreds of thousands gates as random logic. Verification and error localization are traditionally handled separately: for verification the methods of simulation and tautology checking can be used, whereas for error localization, after an error is detected, other dedicated methods are introduced [1,2]. While a lot of work has been done in the field of test synthesis and fault diagnosis in relation to fabrication faults, very little has been done in the field of design error diagnosis [1 5] In [6] a new BDD technique has been proposed, however the explosion of the complexity for some classes ....

.... used, whereas for error localization, after an error is detected, other dedicated methods are introduced [1,2] While a lot of work has been done in the field of test synthesis and fault diagnosis in relation to fabrication faults, very little has been done in the field of design error diagnosis [1 5]. In [6] a new BDD technique has been proposed, however the explosion of the complexity for some classes of circuits puts practical limitations to the use of BDDs in locating design errors. A brief overview of currently available solutions to the diagnosis problem has been given in [2] The ....

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A.M. Wahba, D. Borrione. A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits. J. of Electronic Testing: Theory and Applications 8, 113-127 (1996).

.... one error hypothesis at a time, and returns, for each hypothesis, either the empty set (no change according to this hypothesis can correct the implementation) or a set of proposed changes (figure 1) Our methods for gate error diagnosis in combinational and sequential circuits are published in [11, 12]. This paper focuses on the principles for the automatic identification of connection errors. Start Inverter Error Diagnosis Wrong Gate Diagnosis Missing Connection Diagnosis Extra Connection Diagnosis Bad Connection Diagnosis Candidates Candidates Candidates Candidates Candidates End Figure 1: ....

A. Wahba, and D. Borrione, "A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits," Journal of Electronic Testing: Theory and Applications, Kluwer, Vol. 8, No. 2, April 1996.

....task of locating and correcting the error. We have developed prototype automatic diagnostic tools for logic level designs, which locate the error and suggest a correction with a 100 hit ratio in the case of a single gate or connection errors: CCDS is the diagnoser for combinational circuits [13], and SCDS for sequential circuits [14] 2.5. User Command and Control In designing PREVAIL, the goal was to provide an open and user friendly environment, integrating new formal tools as they become available. Because some verification tasks may take long to execute, multi tasking has been ....

....circuit gates are To appear in Proc. Internat. Conf. on Formal Methods in Computer Aided Design Palo Alto, CA, USA, 6 8 November 1996 9 suspected (i.e. the error may be situated at any gate) The pattern generator selects one of these gates and generates a special pair of test patterns for it [13]. This pair is sent to the simulator, and the specification and the implementation are simulated. The simulation result is sent to the diagnosis engine, that applies the diagnosis rules to limit the number of suspected locations. The reduced set of suspected locations is then sent back to the ....

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Wahba A., Borrione D.: " A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits", to appear in Journal of Electronic Testing: Theory and Applications, Kluwer.

....ces entr ees a NonDiscriminant(C 1 ; C 2 ) Les deux vecteurs sont capables de propager la valeur de sortie de C 1 a au moins une des sorties primaires. Le circuit est ensuite simul e sous l application de ces vecteurs et examin e en utilisant l algorithme de diagnostic par r etro propagation [5]. Cet al..gorithme r eduit progressivement l Ensemble P de chaque composant examin e. Si l Ensemble P(C) d un composant C devient vide, alors C n est pas suspect et il est retir e de l Espace de Recherche. Le meme proc ed e est alors r ep et e avec chaque composant suspect et le nombre de ....

....les memes dans les deux vecteurs. 3. Chaque composant dans Cone(C e ) affecte les autres composants, a l ext erieur de Cone(C e ) seulement au travers d un chemin passant par C e . Pi Les preuves du th eor eme et du corollaire sont omises ici pour des raisons de place; elles sont donn ees dans [5]. Il est a noter que les vecteurs de test sont g en er es dynamiquement pendant la phase de diagnostic, et non dans une phase pr ealable comme le proposent les m ethodes d autres auteurs; notre m ethode acc el ere le proc ed e, car seuls les vecteurs n ecessaires sont employ es. Notre syst eme de ....

A. Wahba, and D. Borrione, "A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits," Journal of Electronic Testing: Theory and Applications, Kluwer, Vol. 8, No. 2, April 1996.

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