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J. H. Lala and L. S. Alger, "Hardware and Software Fault Tolerance: A Unified Architectural Approach," in Proc. 18th International Symposium on Fault-Tolerant Computing, Tokyo, Japan, 1988, pp. 240-245.

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The Time-Triggered Architecture - Kopetz, Bauer (1988)   (18 citations)  (Correct)

.... dependable realtime computer architectures for safety critical applications started more than thirty years ago with the design of the STAR computer [2] and the two projects SIFT [3] and FTMP [4] These projects were carefully evaluated and gave rise to new designs about ten years later: FTPP [5], MAFT [6] and the architectural concepts of the AIRBUS flight control system [7] In 1992 the first paper on SAFEbus [8] the architecture that was later deployed in the Boeing 777 aircraft for flight control, became available. In excellent publications by Lala [9] Avizienis [10] and the books ....

J. Lala and L. Alger. Hardware and Software Fault Tolerance: A Unified Architectural Approach. In Proceedings of the 18th International Symposium on Fault Tolerant Computing, pages 240--245, 1988.


Definition and Evaluation of Adaptive.. - Xu, Di..   (Correct)

.... varying environment, and so any of our results and conclusions is not necessarily true for other supporting environments (e.g. a system that only supports a single application) There is some similar work on the definition and analysis of hardware and software fault tolerant architectures [3] 8][9]. In particular, Laprie, Arlat, Beounes and Kanoun [3] defined a set of hybrid fault tolerant architectures and evaluated three of them. Dugan and Lyu [10] used a combination of fault tree and Markov modeling to analyze three hybrid faulttolerant architectures derived respectively from RB, NVP and ....

J.H. Lala and L.S. Alger, "Hardware and Software Fault Tolerance: A Unified Architectural Approach," Proc. 18th. IEEE International Symposium on Fault-Tolerant Computing, 1988, pp. 240-245.


The Methodology of N-Version Programming - Avizienis (1995)   (7 citations)  (Correct)

.... Newcastle RB investigation employed both the hardware recovery cache and extensions to the MASCOT operating system as the implementation of the EE [And88] while the distributed RB study employs hardware and a custom distributed operating system [Chu87] Other examples of solutions are found in [Mak84, Lal88, Wal88]. The remaining question is the protection against design faults that may exist in the EE itself. For NVS this may be accomplished by N fold diverse implementation of the NVX. To explore the feasibility of this approach, the prototype DEDIX environment has undergone 40 AVI ZIENIS formal ....

J. H. Lala and L. S. Alger. Hardware and software fault tolerance: a unified architectural approach. In Digest of 18th FTCS, pages 240--245, Tokyo, Japan, June 1988.


Fault Injection Based Assessment of Fail-Silence.. - Stott, Speirs.. (2000)   (Correct)

....fault tolerant middleware caused by the overheads imposed by redundancy management protocols. In SIFT, for instance, redundancy management protocols can consume as much as 80 of the processor throughput[15] Hybrid solutions have been proposed to circumvent this problem. MAFT[9] FTP AP[12], and Delta 4[16] hybrid architectures structured around a micro instruction synchronized hard core on top of which conventional processors are replicated. The micro instruction synchronized hard core is responsible for executing redundancy management functions (e.g. message voting) This ....

J. H. Lala and L. S. Alger, "Hardware and software fault tolerance: A unified architecture approach," in Proc. of the 18th Int'l Symp. on Fault-Tolerant Computing (FTCS-18), pp. 240--245, June 1988.


A Technique to Analyze the Tolerance to Transient.. - Bernat, Miro-Julia..   (Correct)

....bounded. With these constraints, upper bounds on the worst case response times of the tasks can be found. Existing faulttolerant architectures designed so that they can run NVP software either meet, or can easily be made to meet the constraints. These include centralized RX s, in the style of [9] [8], or distributed ones in the style of [12] The rest of this paper is structured as follows. In the following section, the fault tolerant architecture and the real time process model is introduced. In section 3, the formulation to compute the worst case response times of the tasks is presented. ....

Jaynarayan H. L. and L. S. Alger. Hardware and software faulttolerance: A unified architectural approach. In 18th International Symposium on Fault-Tolerant Computing, pages 240--245, June 1988.


Definition and Evaluation of Adaptive.. - Xu, Di..   (Correct)

.... varying environment, and so any of our results and conclusions is not necessarily true for other supporting environments (e.g. a system that only supports a single application) There is some similar work on the definition and analysis of hardware and software fault tolerant architectures [3] 8][9]. In particular, Laprie, Arlat, Beounes and Kanoun [3] defined a set of hybrid fault tolerant architectures and evaluated three of them. Dugan and Lyu [10] used a combination of fault tree and Markov modeling to analyze three hybrid faulttolerant architectures derived respectively from RB, NVP and ....

J.H. Lala and L.S. Alger, "Hardware and Software Fault Tolerance: A Unified Architectural Approach," Proc. 18th. IEEE International Symposium on Fault-Tolerant Computing, 1988, pp. 240-245.


Specialized N-Modular Redundant Processors in Large-Scale.. - Ling Yen (1996)   (Correct)

.... the course of the SIFT (Software Implemented Fault Tolerance) project [16] the potential of encountering malicious Byzantine failures was recognized and a Byzantine agreement protocol was developed to deal with it [11, 16] Following SIFT, several systems, such as FTP (Fault Tolerant Processor) [9, 10], FTPP (Fault Tolerant Parallel Processors) 3] and MAFT (Multicomputer Architecture for Fault Tolerance) 6, 15] implemented a Byzantine resilient core to handle malicious failures. However, each of these existing approaches has some of the following limitations: 1) a significant overhead in ....

....transient event (e.g. a large burst of electromagnetic noise) that might induce correlated failures in multiple units. However, the SIFT system requires the application to be structured as time frame structures which imposes constraints on the application. Several subsequent systems, such as FTP [10], FTPP [3] and MAFT [6] implemented a Byzantine resilient core to tolerate malicious failures under the LS LS model (at the application level) Among these systems, FTP does not address the issue of parallel task execution, FTPP was designed for functional programming without a shared state ....

J.H. Lala and L.S. Alger, "Hardware and software fault tolerance: A unified architectural approach, " 18th Intl. Symp. on Fault-Tolerant Computing, Tokyo, Japan, June 1988, pp. 240-245.


System-Level Reliability and Sensitivity Analyses for Three.. - Dugan, Lyu (1993)   (Correct)

....Distributed Recovery Blocks (DRB) scheme [12] combines both distributed processing and Recovery Block (RB) 20] concepts to provide a unified approach to tolerating both hardware and software faults. Architectural considerations for the support of N Version Programming (NVP) 1] were addressed in [14], in which the FTP AP system is described. The FTP AP system achieves hardware and software design diversity by attaching application processors (AP) to the byzantine resilient hard core Fault Tolerant Processor (FTP) N Self Checking Programming (NSCP) 16] uses diverse hardware and software in ....

Jaynarayan H. Lala and Linda S. Alger. Hardware and software fault tolerance: A unified architectural approach. In Proc. IEEE Int. Symp. on Fault-Tolerant Computing, FTCS-18, pages 240--245, June 1988.


Optimal Discrimination between Transient and Permanent Faults - Pizza, al. (1998)   (Correct)

.... faults, spanning from simple retry to rather sophisticated off line error log audit and trend analysis [4, 6] Heuristics are suggested by intuitive reasoning, and then validated by experiment or modelling (see e.g. 1] for an assessment of a heuristic via modelling) Most on line techniques [1, 5, 8, 12, 13] use thresholding schemes. They count errors, and when the count crosses a pre set threshold a permanent fault is assumed. In contrast to the wide application of heuristics, we have found no previous work stating this decision problem in clear probabilistic terms. Interestingly, a rigorous ....

J. H. Lala and L. S. Alger, "Hardware and Software FaultTolerance: a Unified Architectural Approach", in Proc. FTCS-18, Tokyo, 1988, pp. 240-245.


System Reliability Analysis of an N-version Programming.. - Dugan, Lyu (1993)   (9 citations)  (Correct)

....Distributed Recovery Blocks (DRB) scheme [4] combines both distributed processing and Recovery Block (RB) 8] concepts to provide a unified approach to tolerating both hardware and software faults. Architectural considerations for the support of N version programming (NVP) 1] were addressed in [5], in which the FTP AP system is described. The FTP AP system achieves hardware and software design diversity by attaching application processors (AP) to the byzantine resilient hard core Fault Tolerant Processor (FTP) N self checking programming (NSCP) 6] uses diverse hardware and software in ....

Jaynarayan H. Lala and Linda S. Alger. Hardware and software fault tolerance: A unified architectural approach. In Proc. IEEE Int. Symp. on Fault-Tolerant Computing, FTCS-18, pages 240-- 245, June 1988.


Evacuation: A software strategy to support fault-tolerant.. - Colley Aghanya   (Correct)

....of hardware fault tolerance (e.g. the FTMP system[17] or software fault tolerance (e.g. recovery blocks[8] or n version programming[9] in multiprocessor systems. Some architectures have even been designed to tolerate both hardware and software faults simultaneously (e.g. the FTP AP system[14]) Transputer based fault tolerant systems also exist, including the Mars 94 architecture[16] and FTMTA system[12] A problem with most of these designs is that they are either application specific, or constrain an application designer to a particular set of network topologies. The ....

J. H. Lala and L. S. Alger, Hardware and Software fault-tolerance: A unified architectural approach, Digest of Papers, IEEE 18th Symposium on Fault-Tolerant Computer Systems, 1988, pp240-245


Implementing Fail-Silent Nodes For Distributed Systems - Brasileiro Ezhilchelvan (1996)   (7 citations)  (Correct)

....node will be capable of working at nearly the same speed as its constituent processors) In SIFT for instance, redundancy management protocols can consume as much as 80 of the processor throughput [15] Hybrid solutions have been proposed to circumvent this problem. MAFT [10] FTP AP [13], and Delta 4 [16] are hybrid architectures that share the same basic design. These architectures are structured around a micro instruction synchronised hard core, on top of which conventional processors are replicated. The micro instruction synchronised hard core is responsible for executing ....

J.H. Lala, and L.S. Alger, "Hardware and Software Fault Tolerance: A Unified Architectural Approach," Digest of Papers, FTCS-18, Tokyo, Japan, June 1988, pp. 240-245.


Threshold-Based Mechanisms to Discriminate.. - Bondavalli.. (1998)   (4 citations)  (Correct)

No context found.

J. H. Lala and L. S. Alger, "Hardware and Software Fault Tolerance: A Unified Architectural Approach," in Proc. 18th International Symposium on Fault-Tolerant Computing, Tokyo, Japan, 1988, pp. 240-245.


Software Fault Tolerance: A Tutorial - Torres-Pomales (2000)   (Correct)

No context found.

Jaynarayan H. Lala and Linda S. Alger, Hardware and Software Fault Tolerance: A Unified Architectural Approach, Digest of Papers FTCS-18: The Eighteenth International Symposium on Fault-Tolerant Computing, June 1988, pp. 240 - 245.


An Architecture for Constructing Faulttolerant Transputer Systems - Colley And   (Correct)

No context found.

J. H. Lala and L. S. Alger, Hardware and software fault-tolerance: A unified architectural approach, Digest of Papers, IEEE 18th Symposium on Fault-Tolerant Computer Systems, 1988, pp240-245

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