Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200-210, Chicago, Illinois, April 18-21, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....by providing more reliable information in the common case. However, the speculative nature of our schemes causes the analysis results to be not always correct. This means that any optimization performed using this speculative analysis will be speculative as well. Speculative optimizations [21, 17, 22, 20, 27] have been widely used in the compiler world for reducing the overall execution time of programs. The key idea behind speculation is breaking the original program sequence by executing a (possibly unsafe) better reordering of instructions, corresponding to the most likely execution paths. Since ....

....Discussion of speculative optimizations as well as check and recovery mechanisms are, however, beyond of the scope of this paper. In general, speculative alias analysis is particularly well suited to be used in combination with speculative optimizations based on reordering memory operations [21, 17, 22, 27], including those related to the IA 64 architecture [5] An example of such optimizations can be seen in Figure 6. By using the new status of likely independent (see Section 3.3) our speculative disambiguator not only provides information about which instructions are likely to be moved, but ....

[Article contains additional citation context not shown here]

A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Symposium on Computer Architecture, pages 200-210, Chicago, Illinois, Apr. 1994. ACM SIGARCH.

....level parallel processing on VLIW processors. The point of these systems is to allow trace scheduling compilers more flexibility to statically reorder memory instructions. Nicolau [89] proposed inserting explicit address comparisons followed by branches to off trace fix up code. Huang et al. [52] extended this idea to use predicated instructions to help parallelize the comparison code. The problem with this approach is that it requires m n comparisons if there are m loads being speculatively moved above n stores. This problem can be alleviated using a small hardware set associative table, ....

Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA), pages 200--210, Chicago, Illinois, April 1994.

....interference test, c) coherence test. reliable information in the common case. However, the speculative nature of our schemes causes the analysis results to be not always correct. That is, optimization performed using speculative analysis will be speculative as well. Speculative optimizations [19, 15, 20, 18, 25] have been widely used in the compiler world for reducing the overall execution time of programs. The key idea behind speculation is breaking the original program sequence by executing a (possibly unsafe) better reordering of instructions, corresponding to the most likely execution paths. Since ....

....Discussion of speculative optimizations as well as check and recovery mechanisms are, however, beyond of the scope of this paper. In general, speculative alias analysis is particularly well suited to be used in combination with speculative optimizations based on reordering memory operations [19, 15, 20, 25], including those related to the IA 64 architecture [4] An example of such optimizations can be seen in Figure 5. By using the new status of likely independent , our speculative disambiguator not only provides information about which instructions are likely to be moved, but also which ones are ....

[Article contains additional citation context not shown here]

A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Symposium on Computer Architecture, pages 200--210, Chicago, Illinois, Apr. 1994. ACM SIGARCH.

....level parallel processing on VLIW processors. The point of these systems is to allow trace scheduling compilers more flexibility to statically reorder memory instructions. Nicolau [39] proposed inserting explicit address comparisons followed by branches to off trace fixup code. Huang et al. [25] extended this idea to use predicated instructions to help parallelize the comparison code. The problem with this approach is that it requires m n comparisons if there are m loads being speculatively moved above n stores. This problem can be alleviated using a small hardware set associative table, ....

A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA), pages 200--210, Chicago, Illinois, Apr. 1994.

....CFE] addresses a subset of our problem: detection of constant or near constant variables or instruction operands. Such information can support runtime specialization where the program branches to a specialized version if a variable value is as expected. Runtime disambiguation [Nic89, SHZ 94, HSS94] has a particular focus on pointer aliasing to support optimization; for pairs of pointers that profiling shows are rarely aliased, runtime reductions of 16 77 have been realized [Nic89] Static inference. Most pointer analysis research addresses determining alias or points to relations. Such ....

Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In ISCA, pages 200--210, Chicago, Illinois, April 18--21, 1994.

....move freely past joins and downwards past splits, it is not in general safe to move instructions upwards past a conditional branch as this can destroy the intended semantics of the program. Three specific restrictions on upward motion of an instruction I past a branch B are well known ( Chang91] [Huang94], Chang95] Smith90] 1. I must not cause an exception. 2. I must not overwrite the value of a register that is needed by some other successor of B. 3. I must not alter system memory. On conventional architectures, I can only be moved upwards past B if all three of the above conditions are ....

Andrew S. Huang, Gert Slavenburg, John Paul Shen, Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation , Proc. ISCA 94, pp. 200210.

....ensuring program correctness. These can be divided into four categories: static compiler techniques in which disambiguation is statically performed by the compiler; software only dynamic disambiguation, in which the compiler inserts specific disambiguation code into the command stream [Nico89][Huan94]; hardware assisted disambiguation where the compiler uses special op codes which assist disambiguation and verification [Gall94] hardware only dynamic disambiguation as proposed by Franklin and Sohi [Fran96] More recently, work on speculative memory disambiguation has been done in industry and ....

A. Huang, G. Slavenburg and P. Shen -- "Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation" -- ISCA-21, July 1994.

....the data contained in the store are used instead of the data obtained by the load. This method is very similar to preload register updating, and makes generation of the extra load instruction unnecessary. 3.2. 4 Speculative disambiguation Huang et al. have proposed speculative disambiguation [39], a combined hardware and compiler technique to allow aggressive code reordering using predicated instructions. It is similar to run time disambiguation, but employs compiler techniques that allow both a load and its dependent instructions to bypass an ambiguous store. The method also allows two ....

A. S. Huang, G. Slavenburg, and J. P. Shen, "Speculative disambiguation: A compilation technique for dynamic memory disambiguation," in Proceedings of the 21st International Symposium on Computer Architecture, pp. 200--210, April 1994.

....compiler group at University of Illinois uses the approach of instrumenting user code and collecting aliasing frequencies at run time [Joh95] Nic89] proposed a run time disambiguation technique for antialiasing of indirect memory references that cannot normally be disambiguated at compile time. [HSS94] proposed a dynamic memory disambiguation technique for control speculative loads. In this paper, we focus on the memory references from array elements. The question that we try to answer is that if two array memory references may alias with each other, what is the likelihood of this aliasing ....

A. S. Huang, G. Slavenburg, and J. P. Shen, "Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation, " In Proc.of the 21st Annual Int'l Symp. on Computer Architecture, pp. 200-210, April 1994.

.... shadow versions of the variables, either sequentially, or in parallel with the aid of critical sections as in [49] Another significant contribution to this field is the work of Nicolau [32] Run time disambiguation has been recently used in optimizing codes for instruction level parallelism [18, 17]. Their idea is to speculatively execute code very aggressively (out of order) despite the fact that some memory locations (few) could cause unsatisfied data dependences. The offending addresses which are used out of order are stored until all potential hazards have been cleared. If an error is ....

A.S. Huang, G. Slavenburg, and J.P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200--210, Chicago, IL, April 1994.

....CFE99] addresses a subset of our problem: detection of constant or nearconstant variables or instruction operands. Such information can permit run time specialization: the program branches to a specialized version if a variable value is as expected. Run time disambiguation [Nic89, SHZ 94, HSS94] is similar, though it focuses on pointer aliasing. Many optimizations are valid only if two pointers are known not to be aliased. Although static determination of that property is beyond the state of the art, it can be checked at runtime in order to use a specialized version of the code. For ....

Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200--210, Chicago, Illinois, April 18--21, 1994. 34

....focus on the data collection aspect. However since our focus is on how to exploit predictions, we do not discuss this domain any further. Proposals to add value prediction units to the execution engines of future processors focused primarily on exploiting value locality at runtime. Huang et al. [6] discuss the use of prediction information in the context of a processor with support for predicated execution. Moshovos et al. 8] present a proposal to allow speculation of memory dependences in a variant of the Multiscalar Architecture. However as the cost (and cycle impact) of hardware support ....

A. Huang, G. Slavenburg, and J. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proc. ISCA 94, pages 200--210. ACM/IEEE, ACM, April 1994.

....loop and the loop is re executed serially. This form of speculative execution is different from the commonly proposed for advanced uniprocessors. Indeed, much work has been done in uniprocessors trying to issue loads ahead of stores even though the addresses of the locations accessed are unknown [7, 10, 15, 16]. This type of speculation is orthogonal to our work. Our framework exploits parallelism across processors in a multiprocessor. It can use these traditional techniques within each thread. We are effectively adding a second dimension of speculation. There are several advantages to our framework. A ....

A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200--210, April 1994.

....always aliased have been appropriately renamed and that objects that are never aliased are placed in different alias sets. Formal parameters are analyzed for aliasing and placed into alias sets using an algorithm developed by Cooper [Coo85] There are many solutions to the ambiguous alias problem [HSS94, DGS93, Chi91, CCK90, HeS90, Nic89, ChD89] but we focus only on CReg hardware and compiler techniques in this paper. The remainder of the paper covers CReg instruction set modifications and hardware design (Section 2) CReg compilation techniques (Section 3) experimental results and analysis (Section 4) and a summary (Section 5) 2 ....

A. Huang, G. Slavenburg, and J. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In The 21 st Annual International Symposium on Computer Architecture, pages 200--210. IEEE, April 18 -- 21 1994. Chicago, IL.

....CFE] addresses a subset of our problem: detection of constant or near constant variables or instruction operands. Such information can support runtime specialization where the program branches to a specialized version if a variable value is as expected. Runtime disambiguation [Nic89, SHZ 94, HSS94] has a particular focus on pointer aliasing, since many optimizations are valid only if two pointers are known not to be aliased and aliasing is easy to check at runtime. For pairs of pointers that are shown by profiling to be rarely aliased, runtime reductions of 16 77 have been realized ....

Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200--210, Chicago, Illinois, April 18--21, 1994.

....restrictions on parallel issue. Recent work has focused primarily on reducing the latency of specific types of instructions (usually loads from memory) by rearranging pipeline stages [9, 10] initiating memory accesses earlier [11] or speculating that dependences to earlier stores do not exist [12, 13, 14, 15]. The most relevant prior work in the area of eliminating data flow dependences consists of the Tree Machine [16,17] which uses a value cache to store and look up the results of recurring arithmetic expressions to eliminate redundant computation (the value cache, in effect, performs common ....

....location. An example of the former is speculative disambiguation, which optimistically assumes that an earlier definition does not alias with a current use, and provides a mechanism for checking the accuracy of that assumption. Speculative disambiguation has been implemented both in software [13] as well as in hardware [12, 14, 15] Another example of this type of speculation occurs implicitly in most control speculative processors, whenever execution proceeds speculatively past a join in the control flow graph where multiple reaching definitions for a storage location are live [1] By ....

A. S. Huang, G. Slavenburg, and J. P. Shen. "Speculative disambiguation: A compilation technique for dynamic memory disambiguation." In Proceedings of the 21st International Symposium on Computer Architecture, pages 200--210, Chicago, IL, April 1994.

....m emoire concern es ne sont pas les memes et qu il n y a pas de d ependances bien sur. Des techniques ont et e propos ees pour ex ecuter sp eculativement des lectures en pariant sur le fait qu il n y aurait pas d alias avec les ecritures en attente et dont l adresse n est pas encore connue [5] 6][8]. On appelle cette technique d esambiguation m emoire . Les lectures sont donc ex ecut ees meme si l adresse des ecritures pr ec edentes ne sont pas connues mais la donn ee lue attend dans la station de r eservation que les adresses des ecritures pr ec edentes soient toutes connues avant de la ....

....Often, several stores are waiting in reservation stations for their operands being calculated and, thus cannot be bypassed since their addresses are not known. Some work has been done on techniques for speculating on the absence of alias with previous stores in order to execute loads earlier[5] 6][8] and is refered as memory disambiguation. Loads are executed even if some preceding stores are not known but the loaded data waits in the reservation station until addresses of all preceding stores are known. This scheme gives a little performance gain and has been considered in our baseline ....

A.S. Huang, G. Slavenburg, J.P. Shen, Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation, 21st Annual International Symposium on Computer Architecture, April 1994.

....papers on dynamic and static branch prediction techniques have been published. The problem of data speculation has not received as much attention as the problem of control speculation. While the problem of ensuring correct execution while carrying out data speculation has received some attention [1,12,13,14], the issue of improving the accuracy of data speculation, especially dynamic techniques to do so, has not received any attention at all. This paper is concerned with dynamic techniques for improving the accuracy of data speculation. In Section 2, we present the problem of data speculation and ....

....semantics. Precautions must be taken to ensure that I3 executes after I1 in any partially ordered execution schedule. The means for detecting erroneous data speculation and ensuring correct behavior depend upon the processing model. In a VLIW processor, software (run time disambiguation, or RTD [12,14]) or a combination of software and hardware (the Memory Conflict Buffer [1] is responsible for detecting the data misspeculation, and recovery software is responsible for recovering from the misspeculation. 1 In a superscalar processor, memory disambiguation hardware is Figure 1. Load Store ....

[Article contains additional citation context not shown here]

A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proc. 21st Annual Symposium on Computer Architecture, pages 200--210, May 1994.

....level parallel processing on VLIW processors. The point of these systems is to allow tracescheduling compilers more flexibility to statically reorder memory instructions. Nicolau [27] proposed inserting explicit address comparisons followed by branches to off trace fixup code. Huang et al. [15] extended this idea to use predicated instructions to help parallelize the comparison code. The problem with this approach is that it requires m Theta n comparisons if there are m loads being speculatively moved above n stores. This problem can be alleviated using a small hardware set associative ....

Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA), pages 200--210, Chicago, Illinois, April 1994.

....restrictions on parallel issue. Recent work has focused primarily on reducing the latency of specific types of instructions (usually loads from memory) by rearranging pipeline stages [Jou88] initiating memory accesses earlier [AS95] or speculating that dependences to earlier stores do not exist [HSS94, GCM 94] In [LWS96] Lipasti et al. introduce the notion of value locality defined as the recurrence of previouslyseen values and demonstrate a technique Load Value Prediction, or LVP for predicting the results of load instructions at dispatch by exploiting the affinity between load ....

....fashion (or, when in doubt, dependences are pessimistically assumed to exist) Ad hoc attempts to relax the serialization requirements of the strong dependence model have appeared sporadically as modern computer architecture has evolved. For example, techniques like speculative disambiguation [HSS94, GCM 94] can temporarily violate data dependences before those dependences are known. Similarly, branch prediction enables speculative execution of instructions beyond conditional branches, hence violating control dependences temporarily, until the branches resolve. However, conventional ....

Andrew S. Huang, Gert Slavenburg, and John P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st International Symposium on Computer Architecture, pages 200--210, Chicago, IL, April 1994.

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Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200-210, Chicago, Illinois, April 18-21, 1994.

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A. Huang, G. Slavenburg, and J. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st International Symposium on Computer Architecture, pages 200--210, April 1994.

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A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Symposium on Computer Architecture, pages 200--210, Chicago, Illinois, Apr. 1994. ACM SIGARCH.

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A. S. Huang, G. Slavenburg, and J. P. Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proc. ISCA-21, May 1994.

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Andrew S. Huang, Gert Slavenburg, and John Paul Shen. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 200-210, Chicago, Illinois, April 18-21, 1994.

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