W. Ecker, M. Hofmeister, S. Mrz-Rssel, "The Design Cube: A Model for VHDL Design Flow Representation and its Application", In High-Level System Modelling: Specification and Design Methodologies, chapter 3, R. Waxman, J.-M. Berge, editors, Current Issues in Electronic Modelling, vol. 4, Kluwer Academic Publishers, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....pp 226 231, April 11 13, 1994. 7] A. Jantsch, J. berg, P. Ellervee, A. Hemani, A software oriented approach to hardware software co design , poster paper) In Proc. of the Poster session of the International Conference on Compiler Construction (CC 94) Edinburgh, Scotland, April 1994. [8] J. Isoaho, J. berg, A. Hemani, H. Tenhunen, High Level Synthesis in DSP ASIC Optimization , In Proc. of 7th IEEE ASIC Conference and Exhibit (ASIC 94) pp 75 78, Rochester, New York, Sept. 1994. 9] P. Ellervee, A. Jantsch, J. berg, A. Hemani, H. Tenhunen, Exploring ASIC Design Space At ....

....that expands the Y chart or provides a different framework, but none has yet proven to be more advantageous than the other or over the Y chart. The X chart [6] introduce testing as the fourth axis. The Multi level Cybernetic [7] can model design processes and design strategies. The Design Cube [8] is a framework for modelling design activities in the VHDL environment and, unlike the other frameworks, can also model time and data at different levels of abstractions. The Rugby model [9] finally, is slightly different from the other frameworks. It models the Figure 1.2. Domains and levels ....

W. Ecker, M. Hofmeister, S. Mrz-Rssel, "The Design Cube: A Model for VHDL Design Flow Representation and its Application", In High-Level System Modelling: Specification and Design Methodologies, chapter 3, R. Waxman, J.-M. Berge, editors, Current Issues in Electronic Modelling, vol. 4, Kluwer Academic Publishers, 1996.

....mathematical description because it provides more detailed information for implementing the function(s) An algorithm model transforms actual data. Examples of algorithms are quick sort, Givens triangularization, Cholesky matrix decomposition, bisection method, Cooley Tukey FFT, and Winograd FFT [8]. The primary purpose of an algorithm model is to test how well an algorithm designed to implement a mathematical task satisfies the system numerical performance requirements. Algorithm models are also used for determining the numerical effects of finite precision and the parameters of floating ....

....Taxonomy Page 46 of 48 Copyright 1998 VSI Alliance TM Inc. Appendix B: Prior Taxonomies The working group initially compared three existing model definition approaches (shown in Table I) The group considered the features of the existing approaches as a foundation for a VHDL model taxonomy[5] [8]. The Ecker and Madisetti spaces share two axes, while their remaining axes do not directly correspond. Both have an axis for Time resolution and a second axis representing the resolution of data Values in a model. Ecker calls the second axis Value, while Madisetti calls it Format. The Y chart s ....

Ecker, W., Hofmeister, M., "The Design Cube - A Model for VHDL Designflow Representation", Proceedings of the EURO-VHDL, 1992, pp. 752-757.

....Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems Axel Jantsch 1 , Shashi Kumar 2 , Ahmed Hemani 1 1 Royal Institute of Technology, Stockholm, Sweden 2 Indian Institute of Technology, Delhi, India fine grained design manipulations. Design Cube [2] is a framework to model design activities in the VHDL environment and unlike other frameworks also has the capability to model time and data at different levels of abstraction. However, it lacks the ability to represent the physical implementations. While explicitly representing Time and Data in ....

....to be reactive real time systems with soft or hard real time constraints. Furthermore, numerous publications [5, 6] on how to model time illustrate that it is not bound to a particular kind of computation, but rather it is independent. In the formulation of the abstraction levels we follow mostly [2] but extend it to software on one hand and include timing con Computation Transistor Logic Block Concurrent Processes System Functions Relations and Instruction Set HW SW HW SW HW SW HW SW Communication Layout Topology Inter Process Communication Structural and Interface Constraints ....

W.Ecker, M.Hofmeister, and S.März-Rössel, "The Design Cube: A Model for VHDL Design Flow Representation and its Application ", in High Level System Modeling: Specification and Design Methodologies, chapter 3, ed. R. Waxman and J.-M. Berge, Current Issues in Electronic Modeling, vol. 4, Kluwer Academic Publishers, 1996.

....chart due to Gajski[10] It depicts the structural, behavioral, and geometrical aspects of a design, and is shown in Figure 2. Another closely related model to the Y chart is the X chart[10] which provides an additional axis for testing. Recently, a new design representation was proposed by Ecker[15] that we will utilize in this paper to illustrate the top down design process (Figure 1) The Y chart is suitable for the design of ASICs, and as such is too low a level in representation, to be able to efficiently model the process of embedded systems design. Indeed, the Y chart includes the ....

....to efficiently model the process of embedded systems design. Indeed, the Y chart includes the concepts of placement and routing that are mature areas in the industry, and not of immediate interest to the systems designer, though necessary for the final stages of design. Ecker s Cube appears to be[15] ideal for representation of a system prototype under design, where one starts from point A and ends with a prototype at point Z (in Figure 1) The Cube relies on three independent orthogonal views of the prototype: ffl The Design View ffl The Timing View ffl The Value View The Ecker Cube can ....

Ecker W., Hofmeister M, "The Design Cube - A Model for VHDL Designflow Representation", Proceedings of the EUROVHDL, 1992, pp 752-757

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