F. C. Chow and J. L. Hennessy. Register allocation by priority-based coloring. SIGPLAN Notices, 19(6):222--232, June 1984. Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of spill code the allocator described by Briggs inserts [5] Some research has modified or even rejected the paradigm of graph coloring to perform allocation. In 1984, Chow and Hennessy described an algorithm they call priority based coloring that relies on heuristically splitting live ranges [18]. 1991 saw the publication of an algorithm by Callahan and Koblenz that seeks to choose the best spills by dividing the problem into pieces based on the loop structure of the CFG, and then combining the results of applying their algorithm to the different pieces [13] In 1992, Proebsting and ....

Fred C. Chow and John L. Hennessy. Register allocation by priority-based coloring. SIGPLAN Notices, 19(6):222--232, June 1984. Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction.

....global method to reducing spill code, called live range splitting. Chaitin style allocators use maximal length live ranges as the basic unit of allocation. It has long been recognized that breaking a live range into smaller pieces may allow some, or all, of the subsequent pieces to be colored [13, 9]. Chow used this observation in his priority based coloring scheme; when his allocator encountered a live range that could not be kept in a register, it broke it into smaller pieces. Briggs experimented with an aggressive form of live range splitting in his Chaitin style allocator [3, Chapter 6] ....

Fred C. Chow and John L. Hennessy. Register allocation by priority-based coloring. SIGPLAN Notices, 19(6):222--232, June 1984. Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction.

....embodies all the ML speci c treatments in the compiler. By contrast, the back end is machine dependent, but it knows almost nothing about ML. It performs instruction selection, reordering of computations, liveness analysis, register allocation by priority based coloring of the interference graph [8], and emission of MIPS assembly code. In the run time system, the main originality is the use of static typing information to supplement the lack of tagging on objects that are not pointers. Traditionally, garbage collectors rely on run time tags to distinguish pointers into the heap from other ....

F. Chow and J. Hennessy. Register allocation by priority-based coloring. SIGPLAN Notices, 19(6), 1984.

....procedures. 3.2 Embedding into speculative context In the following we show an example how engines can be embedded into a speculative context. We use as an example competitive register allocation. Suppose the compiler writer has three register allocators working with the three methods [Cha82] [CH84] [HGAM92] We reuse the view specification from figure 4 for each of these register allocators and also for the speculative composite engine. ENGINE CLASS registeralloc (IN p:RegisterAlloc) SPECULATIVE chaitin(p) chowhenessy(p) hendren(p) SELECT registerallocselector(p) At runtime the ....

F.C. Chow and J.L. Hennessy. Register allocation by priority based coloring. In Proceedings of the ACM SIGPLAN Symp. on Compiler Construction, June 1984.

....and L. Torczon ping from values in the procedure to registers in the target machine; the mapping must observe the constraints. The first graph coloring allocator was built by Chaitin and his colleagues [8] Another approach, called priority based coloring, was described by Chow and Hennessy [10, 11]. These two techniques have formed the core around which a rich literature has emerged (see Section 7) The techniques used in building graph coloring allocators can be improved. In recent years, several important extensions to Chaitin s basic techniques have appeared [2, 30] Nevertheless, ....

.... graph coloring dates from the early 1960 s [28] see Section 7) The first implementation of a graph coloring register allocator was done by Chaitin and his colleagues in the PL.8 compiler [8, 6] Chow and Hennessy later described a priority based scheme for allocation based on a coloring paradigm [10, 11]. Almost all subsequent work on coloring based allocation has followed from one of these two papers. Our own work follows Chaitin s scheme. Any discussion of register allocation will contain several implicit assumptions. For our work, we assume that the allocator works on low level intermediate ....

[Article contains additional citation context not shown here]

Chow, F. C., and Hennessy, J. L. Register allocation by priority-based coloring. SIGPLAN Notices 19, 6 (June 1984), 222--232. In Proceedings of the ACM SIGPLAN '84 Sympos ium on Compiler Construction.

.... the largest single improvement among various compiler optimizations[HP90] Register allocators in many 6 Research Portfolio (External) modern compilers are based on interference graphs and employ the classical graph coloring method originally proposed by Chaitin and improved by others[CAC 81, CH84, BCKT89] This approach has several strengths and is well suited to general purpose register allocation that works even for programs with irregular and complex ow of control. However, this concise and general strategy is sometimes also a weakness of the interference graph approach. From our ....

F. Chow and J. Hennessy. Register Allocation by priority based coloring. In Proceedings of the ACM SIGPLAN'84 Symposium on Compiler Construction. SIGPLAN Notices 19(6), June 1984.

....of physical registers and the instruction cannot be written back. In this case, the instruction is re executed. 2.3. Register Allocation and Spilling The problem of allocating scalar variables to registers, called the register allocation problem, is usually reduced to a graph coloring problem [Chai81, Chai82, Brig92, Chow84], where an optimal solution is well known to be NP complete. Other research has cast the problem as set of constraints passed to an integer programming solver [Good96, Kong98] or bin packing [Blic92] We focus on graph coloring in this work because it is the most common technique for optimizing ....

Frederick Chow and John Hennessy. Register Allocation by Priority-based Coloring. ACM SIGPLAN Notices, pp. 222-232, June, 1984.

....ranges. Live ranges are selected for coloring in order of their priority. Priority functions capture the expected benefit of allocating the live range to on chip resources as opposed to external memory. 5. ProcessNode: The highest priority node is selected for coloring. For each node, just as in [10], a Forbidden set is maintained which indicates the set of colors (resources) that have already been allocated and hence cannot be used for the current node. If there are enough available colors that can satisfy the color requirement for the current node, the node is colored and the Forbidden sets ....

Fred C. Chow and John L. Hennessy. Register allocation by priority--based coloring. In Proceedings of the ACM SIGPLAN 84 Symposium on Compiler Construction, pages 222--232, New York, NY, 1984. ACM.

....Then we present a technique to transform the interference graph to enable better opportunities for coloring in case the coloring scheme blocks. This is followed by an algorithm for allocating configurations which draws from previous work by Chaitin [27, 28] Briggs [19] and Chow and Hennessy [32]. 6.5.7 Interference Live range construction. A live range is an isolated and connected group of nodes in the control flow graph that connects the definitions and uses of a given program variable. Live ranges are discovered by finding connected groups of def use chains. A single def use chain ....

....is not a new concept. However, it has been used only in the context of register allocation in the past. We adapt those techniques which to work in the context of configuration allocation. First, we present a brief survey of past work related to pruning live range range splitting. Chow et. al [32] first proposed live range splitting. When their register allocator fails to assign a color to a live range lr, it splits lr into smaller live ranges, each smaller piece spanning a single basic block over which it is live. To decrease the amount of compensation code, adjacent live ranges are ....

[Article contains additional citation context not shown here]

Fred C. Chow and John L. Hennessy. Register allocation by priority--based coloring. In Proceedings of the ACM SIGPLAN 84 Symposium on Compiler Construction, pages 222--232, New York, NY, 1984. ACM.

....[Ste77a, SS76] 2. Storing registers into contiguous storage can be much faster than storing them into cells scattered in memory. Often there are special machine instructions to do this. 3. Hennessy and Chow found that their register allocator was not as effective with a caller saves convention [CH84] Their measure of e#ectiveness, however, is static, not dynamic. 4. Caller saves increases code size because the code to save registers must be replicated at every call site. The code size is increased even more if registers are stored back into their shadowed cells instead of in contiguous ....

Frederick Chow and John Hennessy. Register allocation by priority-based coloring. In SIGPLAN Symposium on Compiler Construction, pages 222--232, 1984.

....algorithm is applied to global register allocation after local allocation (within basic blocks) has taken place. Global allocation for a live range is therefore restricted to the registers not already used for local allocation within all basic blocks of the live range. 7. 2 Chow Chow and Hennessy [9, 10] restricted their analysis to the unit of a basic block. Their refined cost function is: save(v) 1 N N X i=1 (loadsave uses i storesave defs i Gamma movecost n i ) freq i where loadsave storesave are the savings due to a reference to definition of a variable in a register ....

Frederick Chow and John Hennessy. Register allocation by priority-based coloring. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, volume 19, pages 222--232, June 1984.

....In recent years, the graph coloring paradigm has emerged as one of the techniques of choice for allocation. The first coloring allocator was built by Chaitin and his colleagues at IBM for the PL.8 compiler [3, 4] Chow and Hennessy describe a different approach to allocation via graph coloring [5, 6]. A Chaitin style allocator assumes that the pre allocation code uses an unlimited number of registers we call these virtual registers. It works by constructing an interference graph that models conflicts between the virtual registers. Next, the allocator tries to find a k coloring for the ....

F. C. Chow and J. L. Hennessy. Register allocation by priority-based coloring. In Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction, SIGPLAN Notices, 19(6), pages 222--232, June 1984.

....extended to include 64 bit floating point loads and stores. The MIPS R2000 R3000 has 32 integer registers and 16 64 bit floating point registers [KH92] Using coloring based register 13 CHAPTER 2. DATA BANDWIDTH PROBLEMS 14 allocation, the compiler is able to do reasonably good data buffering [CH84, Mul87] 2.2 Cache Bandwidth Initially on chip caches were small, so the main concern was to reduce the miss rate and the miss penalty. Increased levels of device integration now allow larger on chip caches, resulting in decreased cache miss rates, and multi level caches minimize the first level ....

F. Chow and J. Hennessy. Register Allocation by Priority-Based Coloring. In Conference Proceedings, SIGPLAN Symposium on Compiler Construction, pages 222--232, June 1984.

....they discover a mapping from values in the procedure to registers in the target machine; the mapping must observe the constraints. The first graph coloring allocator was built by Chaitin and his colleagues [8] Another approach, called priority based coloring, was described by Chow and Hennessy [10, 11]. These two techniques have formed the core around which a rich literature has emerged (see Section 7) The techniques used in building graph coloring allocators can be improved. In recent years, several important extensions to Chaitin s basic techniques have appeared [2, 28] Nevertheless, ....

.... graph coloring dates from the early 1960 s [26] see Section 7) The first implementation of a graph coloring register allocator was done by Chaitin and his colleagues in the PL.8 compiler [8, 6] Chow and Hennessy later described a priority based scheme for allocation based on a coloring paradigm [10, 11]. Almost all subsequent work on coloring based allocation has followed from one of these two papers. Our own work follows Chaitin s scheme. Any discussion of register allocation will contain several implicit assumptions. For our work, we assume that the allocator works on low level intermediate ....

[Article contains additional citation context not shown here]

Chow, F. C., and Hennessy, J. L. Register allocation by priority-based coloring. SIGPLAN Notices 19, 6 (June 1984), 222--232. In Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction.

....register assignment decisions is that register resources are over committed and produce many spills when the code provides many opportunities to perform code improvement transformations 2 or the target machine lacks sufficient registers. Even priority based coloring allocation strategies [CH84] are vulnerable under these circumstances because, although they do not explicitly spill, they cannot provide registers to all of the transformations that expected to get them. While these problems are often manageable, they do limit the range of architectures over which a compiler can be ....

F. C. Chow and J. L. Hennessy, Register Allocation by priority-based coloring, ACM SIGPLAN Notices, 19, 6, June 1984, 222-232.

....is repeated on lr until it has one less than the maximum number of colored neighbors. Computing the estimated cost in this step is based on . the total number of occurrences of the variable in the live range, weighted by loop nesting depths and normalized by the length of the live range. [7] (5) Vertices that were previously in the low degree pool may need to transition into the high degree pool because of live range splitting if it is now a neighbor to both lr and lr 1 . Finding a vertex in the high degree subgraph that has the greatest execution time savings determines which live ....

....time savings determines which live range splits. The cost of building the interference graph makes this algorithm computationally expensive. The complexity for this algorithm is O(k(l k) where k represents the maximum number of registers (colors) and l represents the number of live ranges[7]. We use a form of live range splitting in our modified supertrace register allocation algorithm. We chose to implement live range splitting by renaming variables. Chapter 5 contains the details of our implementation. Multiple Register Operands Language constraints (C unions, volatile variables ....

Chow, F., Hennessey, J., "Register Allocation by Priority-Based Coloring", ACM SIGPLAN `84 Symposium on Compiler Construction, pp. 222-232, 1984.

....binding is propagated to the exit VLM. Figure 9 16: Resolution of a delayed binding 10 Instruction scheduler Our instruction scheduler transforms a trace of IL2 operations into a schedule of wide instructions; it encompasses both the scheduling and register allocation phases of other compilers [16, 32, 34, 17, 18, 56, 31, 55, 72, 11, 12]. The operations have been lowered to machine level by Phase2. For each operation, the instruction scheduler must assign registers for the operands, assign a functional unit for the operation, and place the operation in a wide instruction. It performs a three step algorithm. A. Build a data ....

Chow, Frederick and John Hennessy. Register Allocation by Priority-Based Coloring. In Proc. ACM SIGPLAN '84 Symposium on Compiler Construction (Montreal, June 1984). ACM, New York, 1984, pp. 222-232.

....interprocedural pointer analysis is still not mature on the whole, since the feasibility of a fully functional interprocedural pointer analysis algorithm which can accommodate realistic large programs has not been demonstrated in the literature. Unlike function inlining [1] register allocation [2], and SSA analysis [3] interprocedural pointer analysis has not been integrated into commercial compilers. The key issues that need to be addressed by an interprocedural pointer analysis algorithm include the following. We will demonstrate later that our algorithm indeed raises the applicability ....

F. Chow and J. Hennessy, \Register allocation by priority-based coloring," in Proceedings of the SIGPLAN 1984 Symposium on Compiler Construction, pp. 222-232, June 1984.

....parts of the control flow graph, but proved too inefficient for practical use. Register allocators for other compilers frequently allocate disjoint subregions of a variable s lifetime to different registers, and sometimes can even split a variable s lifetime into separately allocatable regions [CH84, CH90], but these systems do not simultaneously support complete source level debugging. We continue to search for some happy medium register allocator that combines some form of flexible position dependent allocation with high allocation speed and compact debugging information. 12.1.4 Inserting ....

Frederick Chow and John Hennessy. Register Allocation by Priority-Based Coloring. In Proceedings of the SIGPLAN '84 Symposium on Compiler Construction, pp. 222-232, Montreal, Canada, June, 1984. Published as SIGPLAN Notices 19(6), June, 1984.

No context found.

F. C. Chow and J. L. Hennessy. Register allocation by priority-based coloring. SIGPLAN Notices, 19(6):222--232, June 1984. Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction.

No context found.

F. C. Chow and J. L. Hennessy. Register allocation by priority-based coloring. In Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction, pages 222--232, Montreal, Quebec, June 1984.

No context found.

Fred C. Chow and John L. Hennessy. Register allocation by priority--based coloring. In Proceedings of the ACM SIGPLAN 84 Symposium on Compiler Construction, pages 222--232, New York, NY, 1984. ACM.

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F. Chow and J. Hennessy, `Register allocation by priority-based coloring', Proceedings of the ACM SIGPLAN Symposium on Compiler Constructions, June 1984.

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F. Chow and J. Hennessy, `Register allocation by priority-based coloring', Proceedings of the SIGPLAN Notices '84 Symposium on Compiler Construction, Montreal, Canada, (June 1984), pp. 222--232.

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F. C. Chow. Register Allocation by Priority-based Coloring. In SIGPLAN Conference on Compiler Construction, 1984.

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